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 To all our customers
Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp.
The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Mitsubishi Electric, Mitsubishi Electric Corporation, Mitsubishi Semiconductors, and other Mitsubishi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Note : Mitsubishi Electric will continue the business operations of high frequency & optical devices and power devices.
Renesas Technology Corp. Customer Support Dept. April 1, 2003
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER 740 FAMILY / 7470 SERIES
7480 Group 7481 Group
User's Manual
Keep safety first in your circuit designs! Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials These materials are intended as a reference to assist our customers in the selection of the Mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Mitsubishi Electric Corporation or a third party. Mitsubishi Electric Corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts or circuit application examples contained in these materials. All information contained in these materials, including product data, diagrams and charts, represent information on products at the time of publication of these materials, and are subject to change by Mitsubishi Electric Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for the latest product information before purchasing a product listed herein. Mitsubishi Electric Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. The prior written approval of Mitsubishi Electric Corporation is necessary to reprint or reproduce in whole or in part these materials. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. Please contact Mitsubishi Electric Corporation or an authorized Mitsubishi Semiconductor product distributor for further details on these materials or the products contained therein.
Preface
This user's manual of the Mitsubishi CMOS 8-bit microcomputer 7480 Group and 7481 Group describes the hardware specifications and applications in detail. For software information, refer to SERIES 740 USER'S MANUAL, and for development support tools (assemblers, debuggers, etc.) refer to the manual attached to each tool, as well as data book DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS.
BEFORE USING THIS USER'S MANUAL
1. Manual Contents
This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. q CHAPTER 1 - HARDWARE This chapter describes the features of the microcomputers, the operation of their peripherals, and their electrical characteristics. CHAPTER 2 - APPLICATIONS This chapter describes usage of peripheral functions and application examples of the microcomputers, focusing on the settings of the related registers. CHAPTER 3 - APPENDICES This chapter describes all the control register configurations, and the mask ROM confirmation forms (mask ROM version), the ROM programming confirmation forms (one time PROM version), and the mark specification forms to be submitted at the ordering.
q
q
2. Register Configurations
An example of control register configurations of the 7480 Group and 7481 Group and the description of symbols used in them are explained below.
Contents immediately after system is released from reset (Note 1)
b7 b6 b5 b4 b3 b2 b1 b0
Bit
CPU mode register (CPUM) [Address 00FB16]
Bit attributes (Note 2)
00
b 0 1 2 3 4 5 6 7
Name Fix these bits to `0' Stack page selection bit (Note) Watchdog timer L count source selection bit
Function
At reset 0 0
R O O O O
Undefined
W 0 0 O O x x O x
0 : Zero page 1 : 1 page 0 : f(XIN)/8 1 : f(XIN)/16
0 0
Undefined
Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (medium-speed mode)
Undefined
Undefined
0
Undefined
O
Undefined
Not implemented. Writing to this bit is disabled. This bit is undefined at reading.
Note: In the products whose RAM size is 192 bytes or less, set this bit to `0'.
indicates the bit which is not implemented. Notes 1: Contents after system is released from reset 0: `0' after system is released from reset 1: `1' after system is released from reset undefined: undefined after system is released from reset 2: Bit attributes R (Read) O: Read enabled x: Read disabled Undefined: Undefined at reading 0: `0' at reading 1: `1' at reading W (Write) O: Write enabled x: Write disabled 0: Fixed to `0' : This bit can be set to `0' by software, but cannot be set to `1'.
Table of contents
Table of Contents
CHAPTER 1 HARDWARE
1.1 Product Summary ................................................................................................................. 1-2 1.2 Group Expansion .................................................................................................................. 1-3 1.3 Performance Overviews ....................................................................................................... 1-6 1.4 Pinouts .....................................................................................................................................1-8 1.5 Pin Descriptions .................................................................................................................. 1-10 1.6 Functional Block Diagrams ............................................................................................... 1-12 1.7 Central Processing Unit (CPU) ........................................................................................ 1-15 1.7.1 Accumulator (A) ........................................................................................................... 1-16 1.7.2 Index Register X (X) ................................................................................................... 1-16 1.7.3 Index Register Y (Y) ................................................................................................... 1-16 1.7.4 Stack Pointer (S) ......................................................................................................... 1-16 1.7.5 Program Counter (PC) ................................................................................................ 1-18 1.7.6 Processor Status Register (PS) ................................................................................. 1-18 1.8 Access Area ......................................................................................................................... 1-20 1.8.1 Zero Page (Addresses `000016' through `00FF16') .................................................. 1-21 1.8.2 Special Page (Addresses `FF0016' through `FFFF16')............................................. 1-21 1.9 Memory Maps ....................................................................................................................... 1-22 1.10 Input/Output Pins .............................................................................................................. 1-26 1.10.1 Block Diagrams .......................................................................................................... 1-26 1.10.2 Registers Associated with I/O Pins ......................................................................... 1-30 1.10.3 I/O Ports ..................................................................................................................... 1-35 1.10.4 Termination of Unused Pins ..................................................................................... 1-38 1.10.5 Notes on Usage ......................................................................................................... 1-39 1.11 Interrupts ............................................................................................................................ 1-41 1.11.1 Block Diagram ............................................................................................................ 1-42 1.11.2 Registers Associated with Interrupt Control ........................................................... 1-43 1.11.3 Interrupt Sources ....................................................................................................... 1-47 1.11.4 Interrupt Sequence .................................................................................................... 1-49 1.11.5 Interrupt Control ......................................................................................................... 1-53 1.11.6 Setting of Interrupts ................................................................................................... 1-54 1.11.7 Notes on Usage ......................................................................................................... 1-56
7480 Group and 7481 Group User's Manual
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Table of contents
1.12 Timer X and Timer Y ........................................................................................................ 1-57 1.12.1 Block Diagram ............................................................................................................ 1-57 1.12.2 Registers Associated with Timer X and Timer Y .................................................. 1-59 1.12.3 Basic Operations of Timer X and Timer Y ............................................................ 1-64 1.12.4 Timer Mode and Event Count Mode ....................................................................... 1-66 1.12.5 Pulse Output Mode .................................................................................................... 1-70 1.12.6 Pulse Period Measurement Mode ........................................................................... 1-74 1.12.7 Pulse Width Measurement Mode ............................................................................. 1-77 1.12.8 Programmable Waveform Generation Mode .......................................................... 1-80 1.12.9 Programmable One-Shot Output Mode ................................................................... 1-84 1.12.10 PWM Mode ............................................................................................................... 1-88 1.12.11 Notes on Usage ....................................................................................................... 1-92 1.13 Timer 1 and Timer 2 ........................................................................................................ 1-95 1.13.1 Block Diagram ............................................................................................................ 1-95 1.13.2 Registers Associated with Timer 1 and Timer 2 ................................................... 1-95 1.13.3 Basic Operations of Timer 1 and Timer 2 ............................................................. 1-98 1.13.4 Timer Mode ................................................................................................................ 1-99 1.13.5 Programmable Waveform Generation Mode ........................................................ 1-102 1.13.6 Notes on Usage ....................................................................................................... 1-106 1.14 Serial I/O .......................................................................................................................... 1-107 1.14.1 Registers Associated with Serial I/O .................................................................... 1-107 1.14.2 Clock Synchronous Serial I/O ................................................................................ 1-114 1.14.3 Clock Asynchronous Serial I/O (UART) ................................................................ 1-126 1.14.4 Bus Arbitration ......................................................................................................... 1-138 1.15 A-D Converter .................................................................................................................. 1-141 1.15.1 Block Diagram of A-D Converter ........................................................................... 1-141 1.15.2 Registers Associated with A-D Converter ............................................................ 1-142 1.15.3 Operations of A-D Converter ................................................................................. 1-144 1.15.4 Setting of A-D Conversion ...................................................................................... 1-146 1.15.5 Notes on Usage ....................................................................................................... 1-147 1.16 Watchdog Timer .............................................................................................................. 1-149 1.16.1 Block Diagram of Watchdog Timer ....................................................................... 1-149 1.16.2 Registers Associated with Watchdog Timer ......................................................... 1-149 1.16.3 Operations of Watchdog Timer .............................................................................. 1-151 1.16.4 Setting of Watchdog Timer ..................................................................................... 1-153 1.16.5 Notes on Usage ....................................................................................................... 1-153 1.17 Reset .................................................................................................................................. 1-154 1.17.1 Reset Operations ..................................................................................................... 1-155 1.17.2 Internal State at Reset ........................................................................................... 1-156 1.17.3 Notes on Usage ....................................................................................................... 1-157
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7480 Group and 7481 Group User's Manual
Table of contents
1.18 Oscillation Circuit ........................................................................................................... 1-158 1.18.1 Block Diagram of Clock Generator ....................................................................... 1-158 1.18.2 Register Associated with Oscillation Circuit ......................................................... 1-159 1.18.3 Oscillation Operations ............................................................................................. 1-160 1.18.4 Oscillator Start-Up Stabilization Time ................................................................... 1-161 1.18.5 Notes on Usage ....................................................................................................... 1-161 1.19 Power Saving Function ................................................................................................. 1-162 1.19.1 Registers Associated with Power Saving ............................................................. 1-164 1.19.2 Stop Mode ................................................................................................................ 1-166 1.19.3 Wait Mode ................................................................................................................ 1-168 1.19.4 Setting of Valid/Invalid of STP and WIT Instructions ......................................... 1-169 1.19.5 Notes on Usage ....................................................................................................... 1-170 1.20 Built-in PROM Version ................................................................................................... 1-171 1.20.1 EPROM Mode .......................................................................................................... 1-172 1.20.2 Pin Descriptions ....................................................................................................... 1-175 1.20.3 Reading, Programming and Erasing of Built-in PROM ....................................... 1-177 1.20.4 Notes on Usage ....................................................................................................... 1-178 1.21 Electrical Characteristics .............................................................................................. 1-180 1.21.1 Electrical Characteristics ......................................................................................... 1-180 1.21.2 Necessary Conditions for Timing and Switching Characteristics ......................1-190 1.21.3 Typical Characteristics of Power Source Current ............................................... 1-190 1.21.4 Typical Characteristics of Ports ............................................................................. 1-194 1.21.5 Typical Characteristics of A-D Conversion ........................................................... 1-196
7480 Group and 7481 Group User's Manual
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Table of contents CHAPTER 2 APPLICATIONS
2.1 Input/Output Pins .................................................................................................................. 2-2 2.2 Timer X and Timer Y ............................................................................................................ 2-4 2.2.1 Application Example of Timer Mode ........................................................................... 2-4 2.2.2 Application Example of Event Count Mode................................................................ 2-6 2.2.3 Application Example of Pulse Output Mode ............................................................... 2-8 2.2.4 Application Example of Pulse Period Measurement Mode .................................... 2-10 2.2.5 Application Example of Pulse Width Measurement Mode ...................................... 2-12 2.2.6 Application Example of Programmable Waveform Generation Mode ................... 2-14 2.2.7 Application Example of Programmable One-Shot Output Mode............................ 2-16 2.2.8 Application Example of PWM Mode .......................................................................... 2-18 2.3 Serial I/O ............................................................................................................................... 2-20 2.3.1 Application Example of Clock Synchronous Serial I/O Transmission ................... 2-20 2.3.2 Application Example of Clock Asynchronous Serial I/O (UART) Reception ....... 2-22 2.3.3 Application Example of Bus Arbitration Interrupt ..................................................... 2-24 2.4 A-D Converter ...................................................................................................................... 2-29 2.4.1 Determination of A-D Conversion Values ................................................................. 2-29 2.4.2 Application of A-D Converter ..................................................................................... 2-30 2.5 Reset ...................................................................................................................................... 2-32 2.6 Oscillation Circuit ............................................................................................................... 2-33 2.6.1 Oscillation Circuit with Ceramic Resonator .............................................................. 2-33 2.6.2 External Clock Input to XIN ........................................................................................ 2-33 2.7 Power-Saving Function ...................................................................................................... 2-34 2.7.1 Application Example of Stop Mode ........................................................................... 2-34 2.7.2 Application Example of Wait Mode ........................................................................... 2-36 2.8 Countermeasures against Noise ...................................................................................... 2-38 2.8.1 Shortest Wiring Length ............................................................................................... 2-38 2.8.2 Connection of Bypass Capacitor across VSS Line and VCC Line ......................... 2-40 2.8.3 Connection of Bypass Capacitor across VSS Line and VREF Line ....................... 2-40 2.8.4 Wiring to Analog Input Pins ....................................................................................... 2-40 2.8.5 Consideration for Oscillator ........................................................................................ 2-41 2.8.6 Setup for I/O Ports ...................................................................................................... 2-42 2.8.7 Providing of Watchdog Timer Function by Software ............................................... 2-43 2.9 Notes on Programming ...................................................................................................... 2-44 2.9.1 Notes on Processor Status Register ......................................................................... 2-44 2.9.2 Notes Concerning Decimal Operation ....................................................................... 2-45 2.9.3 Notes on JMP Instruction ........................................................................................... 2-45 2.10 Differences between 7480 and 7481 Group, and 7477 and 7478 Group .............. 2-46 2.10.1 Functions Added to 7480 Group and 7481 Group ............................................... 2-46 2.10.2 Functions Revised from 7477 Group and 7478 Group ........................................ 2-47 2.11 Application Circuit Examples ......................................................................................... 2-48
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7480 Group and 7481 Group User's Manual
Table of contents CHAPTER 3 APPENDICES
3.1 Control Registers .................................................................................................................. 3-2 3.2 Mask ROM Confirmation Forms ....................................................................................... 3-20 3.3 ROM Programming Confirmation Forms ........................................................................ 3-40 3.4 Mark Specification Forms ................................................................................................. 3-48 3.5 Package Outlines ................................................................................................................ 3-52 3.6 Machine instructions .......................................................................................................... 3-54 3.7 List of Instruction Codes .................................................................................................. 3-64 3.8 SFR Memory Map ................................................................................................................ 3-65 3.9 Pinouts .................................................................................................................................. 3-66
7480 Group and 7481 Group User's Manual
v
List of Figures
List of Figures
CHAPTER 1 HARDWARE
Figure 1.2.1 ROM/RAM Expansion Plan of 7480 Group and 7481 Group (As of September 1997) ............. 1-4 Figure 1.4.1 Pinout of 7480 Group (top view) ........................................................................... 1-8 Figure 1.4.2 Pinout of 7481 Group (top view) ........................................................................... 1-9 Figure 1.6.1 M37480Mx/E8-XXXSP/FP and M37480MxT/E8T-XXXSP/FP Functional Block Diagram ......... 1-12 Figure 1.6.2 M37481Mx/E8-XXXSP, M37481MxT/E8T-XXXSP and M37481E8SS Functional Block Diagram .. 1-13 Figure 1.6.3 M37481Mx/E8-XXXFP, M37481MxT/E8T-XXXFP Functional Block Diagram ...............................1-14 Figure 1.7.1 CPU Internal Registers ......................................................................................... 1-15 Figure 1.7.2 Operation for Pushing onto and Pulling from Stack ......................................... 1-17 Figure 1.8.1 Access Area ........................................................................................................... 1-20 Figure 1.9.1 Memory Maps of 7480 Group and 7481 Group ................................................ 1-23 Figure 1.9.2 Memory Map of SFR Area ................................................................................... 1-24 Figure 1.9.3 Memory Map of Interrupt Vector Area ................................................................ 1-25 Figure 1.10.1 Block Diagrams of Port Pins P0i and P10-P13 .......................................................... 1-27 Figure 1.10.2 Block Diagram of Port Pins P14-P17 ............................................................................... 1-28 Figure 1.10.3 Block Diagrams of Port Pins P2i to P5i .......................................................................... 1-29 Figure 1.10.4 Memory Map of Registers Associated with I/O Pins ...................................... 1-30 Figure 1.10.5 Port Pi Registers (i = 0 to 5) ............................................................................ 1-31 Figure 1.10.6 Port Pi Direction Registers (i = 0, 1, 4, 5) ...................................................... 1-32 Figure 1.10.7 Port P0 Pull-up Control Register ....................................................................... 1-33 Figure 1.10.8 Port P1 Pull-up Control Register ....................................................................... 1-33 Figure 1.10.9 Port P4P5 Input Control Register ..................................................................... 1-34 Figure 1.10.10 Write and Read of I/O Port Pin ...................................................................... 1-35 Figure 1.10.11 Port P4 and P5 Circuit ..................................................................................... 1-37 Figure 1.11.1 Block Diagram of Interrupt Inputs and Key-On Wakeup Circuit ................... 1-42 Figure 1.11.2 Memory Map of Registers Associated with Interrupt Control ........................ 1-43 Figure 1.11.3 Edge Polarity Selection Register ....................................................................... 1-44 Figure 1.11.4 Interrupt Request Register 1 ............................................................................. 1-45 Figure 1.11.5 Interrupt Request Register 2 ............................................................................. 1-45 Figure 1.11.6 Interrupt Control Register 1 ............................................................................... 1-46 Figure 1.11.7 Interrupt Control Register 2 ............................................................................... 1-46 Figure 1.11.8 Operation When Interrupt Request is Accepted .............................................. 1-50 Figure 1.11.9 Processing Time from Interrupt Generation until Execution of Interrupt Service Routine .... 1-51 Figure 1.11.10 Timing at Interrupt Acceptance ....................................................................... 1-51 Figure 1.11.11 Interrupt Control Diagram ................................................................................. 1-53 Figure 1.11.12 Setting of Interrupts (1) .................................................................................... 1-54 Figure 1.11.13 Setting of Interrupts (2) .................................................................................... 1-55
7480 Group and 7481 Group User's Manual
i
List of Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1.12.1 Block Diagram of Timer X and Timer Y .......................................................... 1-58 1.12.2 Memory Map of Registers Associated with Timer X and Timer Y ............... 1-59 1.12.3 Timer X ................................................................................................................. 1-60 1.12.4 Timer Y ................................................................................................................. 1-61 1.12.5 Timer X Mode Register ...................................................................................... 1-62 1.12.6 Timer Y Mode Register ...................................................................................... 1-63 1.12.7 Timer XY Control Register ............................................................................... 1-63 1.12.8 Operation Example in Timer Mode and Event Count Mode ......................... 1-67 1.12.9 Setting of Timer Mode and Event Count Mode (1) ........................................ 1-68 1.12.10 Setting of Timer Mode and Event Count Mode (2) ...................................... 1-69 1.12.11 Operation Example in Pulse Output Mode .................................................... 1-71 1.12.12 Setting of Pulse Output Mode (1) ................................................................... 1-72 1.12.13 Setting of Pulse Output Mode (2) ................................................................... 1-73 1.12.14 Operation Example in Pulse Period Measurement Mode ............................ 1-75 1.12.15 Setting of Pulse Period Measurement Mode ................................................. 1-76 1.12.16 Operation Example in Pulse Width Measurement Mode ............................. 1-78 1.12.17 Setting of Pulse Width Measurement Mode .................................................. 1-79 1.12.18 Operation Example in Programmable Waveform Generation Mode ...........1-81 1.12.19 Setting of Programmable Waveform Generation Mode (1) .......................... 1-82 1.12.20 Setting of Programmable Waveform Generation Mode (2) ........................ 1-83 1.12.21 Operation Example in Programmable One-Shot Output Mode ................... 1-85 1.12.22 Setting of Programmable One-Shot Output Mode (1) .................................. 1-86 1.12.23 Setting of Programmable One-Shot Output Mode (2) .................................. 1-87 1.12.24 Operation Example in PWM Mode .................................................................. 1-89 1.12.25 Setting of PWM Mode (1) ................................................................................ 1-90 1.12.26 Setting of PWM Mode (2) ................................................................................ 1-91 1.12.27 Operation in Timer X or Timer Y at Writes ................................................... 1-92 1.12.28 Operation in Timer X or Timer Y at Reads ................................................... 1-93 1.13.1 Block Diagram of Timer 1 and Timer 2 ........................................................... 1-95 1.13.2 Memory Map of Registers Associated with Timer 1 and Timer 2 ................ 1-95 1.13.3 Timer 1 ................................................................................................................. 1-96 1.13.4 Timer 2 ................................................................................................................. 1-96 1.13.5 Timer 1 Mode Register ....................................................................................... 1-97 1.13.6 Timer 2 Mode Register ....................................................................................... 1-97 1.13.7 Operations in Timer Mode ............................................................................... 1-100 1.13.8 Setting of Timer Mode ...................................................................................... 1-101 1.13.9 Operations in Programmable Waveform Generation Mode ......................... 1-103 1.13.10 Setting of Programmable Waveform Generation Mode (1) ........................1-104 1.13.11 Setting of Programmable Waveform Generation Mode (2) ........................1-105 1.13.12 Operations in Timer 1 and Timer 2 at Reads ............................................. 1-106
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7480 Group and 7481 Group User's Manual
List of Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1.14.1 Memory Map of Registers Associated with Serial I/O.................................. 1-107 1.14.2 Transmit/Receive Buffer Register .................................................................... 1-108 1.14.3 Serial I/O Status Register ................................................................................ 1-109 1.14.4 Serial I/O Control Register ............................................................................... 1-111 1.14.5 UART Control Register ..................................................................................... 1-112 1.14.6 Baud Rate Generator ........................................................................................ 1-113 1.14.7 Bus Collision Detection Control Register ....................................................... 1-113 1.14.8 Block Diagram of Clock Synchronous Serial I/O .......................................... 1-116 1.14.9 Transmit Operation of Clock Synchronous Serial I/O .................................. 1-118 1.14.10 Transmit Timing of Clock Synchronous Serial I/O ...................................... 1-118 1.14.11 Receive Operation of Clock Synchronous Serial I/O ................................. 1-120 1.14.12 Receive Timing of Clock Synchronous Serial I/O ....................................... 1-120 1.14.13 Setting of Clock Synchronous Serial I/O (1) ............................................... 1-121 1.14.14 Setting of Clock Synchronous Serial I/O (2) ............................................... 1-122 1.14.15 Data Transfer Formats in UART ................................................................... 1-128 1.14.16 Block Diagram of UART ................................................................................. 1-129 1.14.17 Transmit Operation of UART ......................................................................... 1-131 1.14.18 Transmit Timing example in UART ............................................................... 1-131 1.14.19 Receive Operation of UART .......................................................................... 1-133 1.14.20 Receive Timing Example in UART ............................................................... 1-133 1.14.21 Setting of UART (1) ........................................................................................ 1-134 1.14.22 Setting of UART (2) ........................................................................................ 1-135 1.14.23 Contention bus system communications ...................................................... 1-138 1.14.24 Block Diagram of Bus Arbitration Interrupt .................................................. 1-138 1.14.25 Timing of Bus Collision Detection ................................................................. 1-139 1.14.26 Setting of Bus Arbitration Interrupt ............................................................... 1-140 1.15.1 Block Diagram of A-D Converter..................................................................... 1-141 1.15.2 Memory Map of Registers Associated with A-D Converter ......................... 1-142 1.15.3 A-D Control Register ......................................................................................... 1-142 1.15.4 A-D Conversion Register .................................................................................. 1-143 1.15.5 Change of A-D Conversion Register and Comparison Voltage during A-D Conversion..... 1-145 1.15.6 Setting of A-D Conversion ............................................................................... 1-146 1.15.7 Internal equivalent circuit of analog input circuit .......................................... 1-148 1.16.1 Block Diagram of Watchdog Timer ................................................................. 1-149 1.16.2 Memory Map of Registers Associated with Watchdog Timer ...................... 1-149 1.16.3 Watchdog Timer H ............................................................................................ 1-150 1.16.4 CPU Mode Register .......................................................................................... 1-150 1.16.5 Internal Processing Sequence during Reset by Watchdog Timer ............. 1-152 1.16.6 Setting of Watchdog Timer .............................................................................. 1-153 1.17.1 Internal Processing Sequence after Reset Release ..................................... 1-155 1.17.2 Internal State at Reset ..................................................................................... 1-156 1.18.1 Block Diagram of Clock Generator ................................................................. 1-158 1.18.2 Memory Map of Register Associated with Oscillation Circuit ...................... 1-159 1.18.3 CPU Mode Register .......................................................................................... 1-159 1.18.4 Oscillator Start-Up Stabilization Time at Power On ..................................... 1-161 1.19.1 Transitions from Power Saving Modes ........................................................... 1-163 1.19.2 Memory Map of Registers Associated with Power Saving .......................... 1-164 1.19.3 STP Instruction Operation Control Register .................................................. 1-164 1.19.4 Edge Polarity Selection Register ..................................................................... 1-165 1.19.5 Operation at Recovery from Stop Mode by Reset Input ............................. 1-166 1.19.6 Operation Example at Recovery from Stop Mode by INT0 Interrupt......... 1-167 1.19.7 Setting of Valid/Invalid of STP and WIT Instructions ................................... 1-169
7480 Group and 7481 Group User's Manual
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List of Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1.20.1 Pinout in EPROM Mode of 7480 Group ........................................................ 1-172 1.20.2 Pinout in EPROM Mode of 7481 Group (1) .................................................. 1-173 1.20.3 Pinout in EPROM Mode of 7481 Group (2) .................................................. 1-174 1.20.4 Programming and Verification of One Time PROM Version .......................1-178 1.21.1 Timing Diagram ................................................................................................. 1-190 1.21.2 Measurement Circuit of Typical Power Source Current Characteristics ... 1-190 1.21.3 VCC-ICC Characteristics (at System Operating in High-Speed Mode) ...... 1-191 1.21.4 VCC-ICC Characteristics (at System Operating in Medium-Speed Mode) . 1-191 1.21.5 VCC-ICC Characteristics (in Wait Mode) ........................................................ 1-192 1.21.6 VCC-ICC Characteristic (in Stop Mode) .......................................................... 1-192 1.21.7 f(XIN)-ICC Characteristics (at System Operating in High-Speed Mode) .... 1-193 1.21.8 f(XIN)-ICC Characteristics (at System Operating in Medium-Speed Mode)1-193 1.21.9 Measurement Circuits of Typical Port Characteristics .................................. 1-194 1.21.10 VOH-IOH Characteristics on P-Channel Side of Programmable I/O Port (CMOS Output) 1-194 1.21.11 VOL-IOL Characteristics on N-Channel Side of Programmable I/O Port (CMOS Output) 1-195 1.21.12 VIL-IIL Characteristics of Pull-up Transistor of Programmable I/O Port (CMOS Output) 1-195 1.21.13 Typical Characteristics of A-D Conversion (1) ............................................ 1-197 1.21.14 Typical Characteristics of A-D Conversion (2) ............................................ 1-198
CHAPTER 2 APPLICATIONS
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 2.1.1 External Circuit for Output Ports ........................................................................... 2-2 2.1.2 Simplified External Circuit Example by Using Level Shift Port and Noise Margin .................. 2-3 2.2.1 Setting Example of Division Ratio ......................................................................... 2-4 2.2.2 Control Procedure Example of 100-ms Processing ............................................ 2-5 2.2.3 Peripheral Circuit Example ..................................................................................... 2-6 2.2.4 Method of Measuring Water Flow Rate ................................................................ 2-6 2.2.5 Control Procedure Example of Measuring Water Flow Rate ............................. 2-7 2.2.6 Peripheral Circuit Example ..................................................................................... 2-8 2.2.7 Setting Example of Division Ratio ......................................................................... 2-8 2.2.8 Control Procedure Example of Buzzer Output .................................................... 2-9 2.2.9 Peripheral Circuit Example ................................................................................... 2-10 2.2.10 Phase Control Procedure Example ................................................................... 2-11 2.2.11 Peripheral Circuit Example ................................................................................. 2-12 2.2.12 Communication Format Example ....................................................................... 2-12 2.2.13 Communications Control Procedure Example .................................................. 2-13 2.2.14 Peripheral Circuit Example ................................................................................. 2-14 2.2.15 Operation Timing Example ................................................................................. 2-14 2.2.16 Control Procedure Example of Motorcycle Engine ......................................... 2-15 2.2.17 Peripheral Circuit Example ................................................................................. 2-16 2.2.18 Operation Timing Example ................................................................................. 2-16 2.2.19 Phase Control Procedure Example ................................................................... 2-17 2.2.20 Peripheral Circuit Example ................................................................................. 2-18 2.2.21 Control Procedure Example of Analog Voltage Output .................................. 2-19
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7480 Group and 7481 Group User's Manual
List of Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 2.3.1 Connection Example ............................................................................................. 2-20 2.3.2 Setting Example of Synchronous Clock ............................................................. 2-20 2.3.3 Timing of Interrupt Control ................................................................................... 2-21 2.3.4 Control Procedure Example of Serial I/O Transmit .......................................... 2-21 2.3.5 Connection Example ............................................................................................. 2-22 2.3.6 Setting Example of Synchronous Clock ............................................................. 2-22 2.3.7 Communication Format ......................................................................................... 2-22 2.3.8 Control Procedure Example of Serial I/O Receive ........................................... 2-23 2.3.9 Connection Example ............................................................................................. 2-24 2.3.10 Setting Example of Synchronous Clock ........................................................... 2-24 2.3.11 Communication Format Example of Simplified SAE J1850 ........................... 2-25 2.3.12 Communication Timing Example ....................................................................... 2-26 2.3.13 Control Procedure Example (1) of LAN Communications .............................. 2-27 2.3.14 Control Procedure Example (2) of LAN Communications .............................. 2-28 2.4.1 Example of Determining A-D Conversion Values.............................................. 2-30 2.4.2 Control Procedure Example of Determining A-D Conversion Values ............. 2-31 2.5.1 Reset Circuit Examples ........................................................................................ 2-32 2.6.1 Oscillation Circuit Example with Ceramic Resonator ........................................ 2-33 2.6.2 External Clock Circuit Example ........................................................................... 2-33 2.7.1 Connection Example ............................................................................................. 2-34 2.7.2 Operation Example in Key-Input Waiting State ................................................. 2-34 2.7.3 Control Procedure Example of Power-Saving in Key-Input Waiting State.... 2-35 2.7.4 Connection Example ............................................................................................. 2-36 2.7.5 Operation Example in Serial I/O Receive Waiting State.................................. 2-36 2.7.6 Control Procedure Example of Power-Saving ................................................... 2-37 2.8.1 Wiring for RESET Pin ........................................................................................... 2-38 2.8.2 Wiring for Clock I/O Pins ..................................................................................... 2-39 2.8.3 Wiring for VPP Pin of One Time PROM and EPROM Version ....................... 2-39 2.8.4 Bypass Capacitor across VSS Line and VCC Line ............................................ 2-40 2.8.5 Bypass Capacitor across VSS Line and VREF Line .......................................... 2-40 2.8.6 Analog Signal Line and Resistor and Capacitor ............................................... 2-40 2.8.7 Wiring for Large Current Signal Line ................................................................ 2-41 2.8.8 Wiring to Signal Line Where Potential Levels Change Frequently ................. 2-41 2.8.9 VSS Patterns on Underside of Oscillator ............................................................ 2-41 2.8.10 Setup For I/O Ports ........................................................................................... 2-42 2.8.11 Watchdog Timer by Software ............................................................................ 2-43 2.9.1 Initialization of Flags in PS .................................................................................. 2-44 2.9.2 Stack Memory Contents after PHP Instruction Execution ................................ 2-44 2.9.3 PLP Instruction Execution .................................................................................... 2-44 2.9.4 Execution of Decimal Operation .......................................................................... 2-45 2.11.1 Application Circuit to Hot-Water Supply Equipment ....................................... 2-48 2.11.2 Application Circuit to Motorcycle Single-Cylinder Engine .............................. 2-49
7480 Group and 7481 Group User's Manual
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List of Figures CHAPTER 3 APPENDICES
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 3.1.1 Port Pi Registers (i = 0 to 5) ................................................................................ 3-2 3.1.2 Port Pi Direction Registers (i = 0, 1, 4, 5) .......................................................... 3-2 3.1.3 Port P0 Pull-up Control Register ........................................................................... 3-3 3.1.4 Port P1 Pull-up Control Register ........................................................................... 3-3 3.1.5 Port P4P5 Input Control Register ......................................................................... 3-4 3.1.6 Edge Polarity Selection Register ........................................................................... 3-5 3.1.7 A-D Control Register ............................................................................................... 3-6 3.1.8 A-D Conversion Register ........................................................................................ 3-6 3.1.9 STP Instruction Operation Control Register ......................................................... 3-7 3.1.10 Transmit/Receive Buffer Register ........................................................................ 3-8 3.1.11 Serial I/O Status Register .................................................................................... 3-8 3.1.12 Serial I/O Control Register ................................................................................... 3-9 3.1.13 UART Control Register ......................................................................................... 3-9 3.1.14 Baud Rate Generator .......................................................................................... 3-10 3.1.15 Bus Collision Detection Control Register ......................................................... 3-10 3.1.16 Watchdog Timer H .............................................................................................. 3-11 3.1.17 Timer X ................................................................................................................. 3-12 3.1.18 Timer Y ................................................................................................................. 3-13 3.1.19 Timer 1 ................................................................................................................. 3-13 3.1.20 Timer 2 ................................................................................................................. 3-14 3.1.21 Timer X Mode Register ...................................................................................... 3-14 3.1.22 Timer Y Mode Register ...................................................................................... 3-15 3.1.23 Timer XY Control Register ................................................................................. 3-15 3.1.24 Timer 1 Mode Register ....................................................................................... 3-16 3.1.25 Timer 2 Mode Register ....................................................................................... 3-16 3.1.26 CPU Mode Register ............................................................................................ 3-17 3.1.27 Interrupt Request Register 1 ............................................................................. 3-18 3.1.28 Interrupt Request Register 2 ............................................................................. 3-18 3.1.29 Interrupt Control Register 1 ............................................................................... 3-19 3.1.30 Interrupt Control Register 2 ............................................................................... 3-19 3.8.1 SFR Memory Map ................................................................................................. 3-65 3.9.1 Pinout of 7480 Group (top view) ......................................................................... 3-66 3.9.2 Pinout of 7481 Group (top view) ......................................................................... 3-67
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List of Tables
List of Tables
CHAPTER 1 HARDWARE
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1.2.1 Supported Products of 7480 Group and 7481 Group .......................................... 1-5 1.3.1 Performance Overview of 7480 Group .................................................................. 1-6 1.3.2 Performance Overview of 7481 Group .................................................................. 1-7 1.7.1 Push and Pull Instructions for Accumulator and Processor Status Register . 1-16 1.7.2 Instructions to Set Flags of Processor Status Register to `1' or `0' ................ 1-19 1.9.1 RAM Area ................................................................................................................ 1-22 1.9.2 ROM Area ................................................................................................................ 1-22 1.10.1 Termination of Unused Pins ................................................................................ 1-38 1.11.1 Interrupt Sources .................................................................................................. 1-41 1.11.2 Interrupt Sources Available for CPU's Return from Stop/Wait Mode ............ 1-52 1.12.1 Relation between Timer Count Periods and Values Set to Timer X and Timer Y ................. 1-65 1.13.1 Relation between Timer Count Periods and Values Set to Timer 1 and Timer 2 .................. 1-99 1.14.1 Clearing Error Flags ........................................................................................... 1-110 1.14.2 Example of Baud Rates ..................................................................................... 1-127 1.14.3 Setting of UART Control Register .................................................................... 1-128 1.14.4 Function of UART Transfer Data Bits .............................................................. 1-129 1.19.1 States of Microcomputer in Power Saving Modes ......................................... 1-162 1.20.1 Supported Built-in PROM Version Products in 7480 Group and 7481 Group (As of September 1997) .................................................................................... 1-171 1.20.2 Pin Functions in EPROM Mode ........................................................................ 1-172 1.20.3 Pin Descriptions (1) ............................................................................................ 1-175 1.20.4 Pin Descriptions (2) ............................................................................................ 1-176 1.20.5 I/O Signals in EPROM Mode ............................................................................ 1-177 1.21.1 Absolute Maximum Ratings of 7480 Group .................................................... 1-180 1.21.2 Recommended Operating Conditions of 7480 Group (1) .............................. 1-180 1.21.3 Recommended Operating Conditions of 7480 Group (2) .............................. 1-181 1.21.4 Electrical Characteristics of 7480 Group (1) ................................................... 1-182 1.21.5 Electrical Characteristics of 7480 Group (2) ................................................... 1-183 1.21.6 A-D Conversion Characteristics of 7480 Group ............................................. 1-184 1.21.7 Absolute Maximum Ratings of 7481 Group .................................................... 1-185 1.21.8 Recommended Operating Conditions of 7481 Group (1) .............................. 1-185 1.21.9 Recommended Operating Conditions of 7481 Group (2) .............................. 1-186 1.21.10 Electrical Characteristics of 7481 Group (1) ................................................. 1-187 1.21.11 Electrical Characteristics of 7481 Group (2) ................................................. 1-188 1.21.12 A-D Conversion Characteristics of 7481 Group ........................................... 1-189 1.21.13 Necessary Conditions for Timing and Switching Characteristics .............. 1-190
CHAPTER 2 APPLICATIONS
Table 2.10.1 Functions added to the 7480 Group and 7481 Group .................................... 2-46 Table 2.10.2 Functions Revised from 7477 Group and 7478 Group ................................... 2-47
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CHAPTER 1 HARDWARE
1.1 Product Summary 1.2 Group Expansion 1.3 Performance Overviews 1.4 Pinouts 1.5 Pin Descriptions 1.6 Functional Block Diagrams 1.7 Central Processing Unit (CPU) 1.8 Access Area 1.9 Memory Maps 1.10 Input/Output Pins 1.11 Interrupts 1.12 Timer X and Timer Y 1.13 Timer 1 and Timer 2 1.14 Serial I/O 1.15 A-D Converter 1.16 Watchdog Timer 1.17 Reset 1.18 Oscillation Circuit 1.19 Power Saving Function 1.20 Built-in PROM Version 1.21 Electrical Characteristics
HARDWARE
1.1 Product Summary
1.1 Product Summary
The 7480 Group and 7481 Group are 8-bit microcomputers fabricated using Mitsubishi's silicon gate CMOS process. They have a simple instruction set with ROM, RAM, and input/output (I/O) interface that are located in the same memory area. These microcomputers contain a serial I/O, an A-D converter, and a watchdog timer on a single chip, so that they are most suitable for control use in automotive controls, office machines, and home appliances. The 7480 Group and 7481 Group offer products with various types and sizes of built-in memories, as well as several choice of packages.
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1.2 Group Expansion
1.2 Group Expansion
The 7480 Group and 7481 Group are included in the 7470 series microcomputers, based on the M37470M2XXXSP. The 7470 series is classified as follows: 7470 series 7470 Group 7471 Group 7477 Group 7478 Group 7480 Group 7481 Group Figure 1.2.1 shows the ROM/RAM expansion plan for the 7480 Group and 7481 Group. Since these products are different only in the type and size of built-in memory, and the number of ports, the most suitable product for user's system can be easily selected. The following products are supported in the 7480 Group and 7481 Group in addition to the mask ROM version. (1) One Time PROM Version This is a programmable microcomputer with built-in programmable ROM (PROM) that can be written to only one time. For details, refer to Section 1.20 Built-in PROM Version. (2) Built-in EPROM Version (with Window) This is a programmable microcomputer with a transparent window on top of its package. Built-in EPROM can be written and erased. For details, refer to Section 1.20 Built-in PROM Version. Table 1.2.1 lists the products currently supported in the 7480 Group and 7481 Group.
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HARDWARE
1.2 Group Expansion
ROM size (bytes)
16 K
M37480M8T-XXXSP/FP M37480E8T-XXXSP/FP M37481M8T-XXXSP/FP M37481E8T-XXXSP/FP M37481E8SS M37480M8-XXXSP/FP M37480E8-XXXSP/FP M37481M8-XXXSP/FP M37481E8-XXXSP/FP
12 K
8K
M37480M4-XXXSP/FP M37480M4T-XXXSP/FP M37481M4-XXXSP/FP M37481M4T-XXXSP/FP
4K
M37480M2T-XXXSP/FP M37481M2T-XXXSP/FP
0
128
256
384
448
RAM size (bytes) : Under development : Under planning
Note: Regarding the products being developed and planned, the development schedule may be reviewed. Regarding the products being planned, the development of them may be stopped.
Figure 1.2.1 ROM/RAM Expansion Plan of 7480 Group and 7481 Group (As of September 1997)
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1.2 Group Expansion
Table 1.2.1 Supported Products of 7480 Group and 7481 Group Product M37480M2T-XXXSP M37480M2T-XXXFP M37480M4-XXXSP M37480M4-XXXFP M37480M4T-XXXSP M37480M4T-XXXFP M37480M8-XXXSP M37480M8-XXXFP M37480M8T-XXXSP M37480M8T-XXXFP M37480E8SP M37480E8FP M37480E8-XXXSP M37480E8-XXXFP M37480E8T-XXXSP M37480E8T-XXXFP M37481M2T-XXXSP M37481M2T-XXXFP M37481M4-XXXSP M37481M4-XXXFP M37481M4T-XXXSP M37481M4T-XXXFP M37481M8-XXXSP M37481M8-XXXFP M37481M8T-XXXSP M37481M8T-XXXFP M37481E8SP M37481E8FP M37481E8-XXXSP M37481E8-XXXFP M37481E8T-XXXSP M37481E8T-XXXFP M37481E8SS Note: Extended Operating Temperature Range Version. 16384 448 I/O ports: 24 Input ports: 12 4096 128 16384 448 8192 256 ROM RAM (bytes) (bytes) 4096 128 I/O Ports Package 32P4B 32P2W-A 32P4B 32P2W-A 32P4B I/O ports: 18 Input ports: 8 32P2W-A 32P4B 32P2W-A (As of September 1997) Remarks Mask ROM version (Note) Mask ROM version Mask ROM version (Note) Mask ROM version Mask ROM version (Note) One Time PROM version (Shipped in blank) One Time PROM version One Time PROM version (Note) Mask ROM version (Note) Mask ROM version Mask ROM version (Note) Mask ROM version Mask ROM version (Note) One Time PROM version (Shipped in blank) One Time PROM version One Time PROM version (Note) Built-in EPROM version
(Including 4 analog 32P4B input pins.) 32P2W-A 32P4B 32P2W-A 32P4B 32P2W-A 32P4B 32P2W-A 42P4B 44P6N-A 42P4B 44P6N-A 42P4B 44P6N-A 42P4B 44P6N-A 42P4B
8192
256
(Including 8 analog 44P6N-A input pins.) 42P4B 44P6N-A 42P4B 44P6N-A 42P4B 44P6N-A 42S1B-A
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1.3 Performance Overviews
1.3 Performance Overviews
Tables 1.3.1 and 1.3.2 list the performance overviews of the 7480 Group and 7481 Group, respectively. Table 1.3.1 Performance Overview of 7480 Group Items Number of Basic Instructions Instruction Execution Time Clock Input Oscillation Frequency M37480M2 ROM M37480M4 Memory Size RAM M37480M8/E8 M37480M2 M37480M4 M37480M8/E8 P0 Input/ Output Ports Input I/O P1 P4 P2 P3 Input/Output Voltage Output Current Performance 71 (69 basic instructions of 740 Family and 2 Multiply and Divide instructions) 0.5 s (the minimum instructions at f(XIN) = 8 MHz) 8 MHz (Max.) 4096 bytes 8192 bytes 16384 bytes 128 bytes 256 bytes 448 bytes 8 bits 8 bits 2 bits 4 bits 4 bits 5V -5 mA to 10 mA (P0, P1: CMOS 3-State Buffer) 10 mA (P4: N-Channel open-drain) 8 bits x 1 16-bit timer x 2 8-bit timer x 2 M37480M2 Subroutine Nesting M37480M4 M37480M8/E8 Interrupt Sources A-D Converter (Successive Comparison Conversion) Clock Generator Watchdog Timer Power Supply Power Dissipation Operating Temperature Range Device Structure M37480Mx/E8-XXXSP M37480MxT/E8T-XXXSP M37480Mx/E8-XXXFP M37480MxT/E8T-XXXFP 64 levels (Max.) 96 levels (Max.) 192 levels (Max.) 5 external, 8 internal, and 1 software interrupt sources 4-channel analog inputs (alternative function of Port 2 pins) Built-in circuit with a feedback resistor; a ceramic resonator external Built-in circuit 2.7 V to 4.5 V (f(XIN) = (2.2 VCC-2) MHz) 4.5 V to 5.5 V (f(XIN) = 8 MHz) 35 mW (typical value at f(XIN) = 8 MHz) -20 C to 85 C (-40 C to 85 C for Extended Operating Temperature Range Version) CMOS Silicon Gate 32-Pin Shrink Plastic DIP 32-Pin Plastic SOP
Input/Output Characteristics Serial I/O Timers
Package
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1.3 Performance Overviews
Table 1.3.2 Performance Overview of 7481 Group Items Number of Basic Instructions Instruction Execution Time Clock Input Oscillation Frequency M37481M2 ROM M37481M4 Memory Size RAM M37481M8/E8 M37481M2 M37481M4 M37481M8/E8 P0 Input/ Output Ports Input Input/Output Characteristics Serial I/O Timers M37481M2 Subroutine Nesting M37481M4 M37481M8/E8 Interrupt Sources A-D Converter (Successive Comparison Conversion) Clock Generator Watchdog Timer Power Supply Power Dissipation Operating Temperature Range Device Structure M37481Mx/E8-XXXSP M37481MxT/E8T-XXXSP Package M37481E8SS M37481Mx/E8-XXXFP M37481MxT/E8T-XXXFP I/O P1 P4 P5 P2 P3 Input/Output Voltage Output Current Performance 71 (69 basic instructions of 740 Family and 2 Multiply and Divide instructions) 0.5 s (the minimum instructions at f(XIN) = 8 MHz) 8 MHz (Max.) 4096 bytes 8192 bytes 16384 bytes 128 bytes 256 bytes 448 bytes 8 bits 8 bits 4 bits 4 bits 8 bits 4 bits 5V -5 mA to 10 mA (P0, P1: CMOS 3-State Buffer) 10 mA (P4, P5: N-Channel open-drain) 8 bits x 1 16-bit timer x 2 8-bit timer x 2 64 levels (Max.) 96 levels (Max.) 192 levels (Max.) 5 external, 8 internal, and 1 software interrupt sources 8-channel analog inputs (alternative function of Port 2 pins) Built-in circuit with a feedback resistor; a ceramic resonator external Built-in circuit 2.7 V to 4.5 V (f(XIN) = (2.2 VCC-2) MHz) 4.5 V to 5.5 V (f(XIN) = 8 MHz) 35 mW (typical value at f(XIN) = 8 MHz) -20 C to 85 C (-40 C to 85 C for Extended Operating Temperature Range Version) CMOS Silicon Gate 42-Pin Shrink Plastic DIP 42-Pin Shrink Ceramic DIP 44-Pin Plastic QFP
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1.4 Pinouts
1.4 Pinouts
Figures 1.4.1 and 1.4.2 show the pinouts of the 7480 Group and 7481 Group, respectively. For the pinouts of the built-in PROM versions used in the EPROM mode, refer to Section 1.20.1 EPROM mode.
Pinout (top view)
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET VCC
Outline 32P4B V1
M37480M8-XXXSP M37480M8T-XXXSP M37480E8-XXXSP M37480E8T-XXXSP
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET VCC
Outline 32P2W-A V2 V 1: The M37480M2T-XXXSP, M37480M4-XXXSP and M37480M4T-XXXSP are also included in the 32P4B packages, respectively. All of these products are pin-compatible. 2: The M37480M2T-XXXFP, M37480M4-XXXFP and M37480M4T-XXXFP are also included in the 32P2W-A packages, respectively. All of these products are pin-compatible. Note: The only differences between the 32P4B package product and the 32P2W-A package product are package outline and absolute maximum ratings.
Figure 1.4.1 Pinout of 7480 Group (top view)
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M37480M8-XXXFP M37480M8T-XXXFP M37480E8-XXXFP M37480E8T-XXXFP
HARDWARE
1.4 Pinouts
Pinout (top view)
P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET P51 P50 VCC
Outline 42P4B V1 42S1B-A (M37481E8SS)
31
33
27
30
28
32
P04 P05 P06 P07 P52 VSS P53 P17/SRDY P16/SCLK P15/TXD P14/RXD
29
26
25
24
23
P03 P02 P01 P00 P43 P42 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1
M37481M8-XXXSP M37481M8T-XXXSP M37481E8-XXXSP M37481E8T-XXXSP M37481E8SS
34 35 36 37 38 39 40 41 42 43 44
22 21 20
M37481M8-XXXFP M37481M8T-XXXFP M37481E8-XXXFP M37481E8T-XXXFP
19 18 17 16 15 14 13 12
P30/INT0 RESET P51 P50 VCC VSS AVSS XOUT XIN VREF P20/IN0
V 1: The M37481M2T-XXXSP, M37481M4-XXXSP and M37481M4T-XXXSP are also included in the 42P4B packages, respectively. All of these products are pin-compatible. 2: The M37481M2T-XXXFP, M37481M4-XXXFP and M37481M4T-XXXFP are also included in the 44P6N-A packages, respectively. All of these products are pin-compatible. Note: The only differences between the 42P4B package product and the 44P6N-A package product are package outline, absolute maximum ratings and the fact that the 44P6N-A package product has the AVss pin.
Figure 1.4.2 Pinout of 7481 Group (top view)
P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1
Outline 44P6N-A
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2
4
7
3
6
5
8
9
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1.5 Pin Descriptions
1.5 Pin Descriptions
Tables 1.5.1 and 1.5.2 list the pin descriptions. For pin functions in the EPROM mode of the built-in PROM version, refer to Section 1.20.2 Pin Descriptions. Table 1.5.1 Pin Descriptions (1) Pin VCC, VSS Name Power source Input/ Output Function * Apply the following voltage to the VCC pin: 2.7 V to 4.5 V (at f(XIN) = (2.2 VCC-2) MHz), or 4.5 V to 5.5 V (at f(XIN) = 8 MHz). * Apply 0 V to the VSS pin. AVSS Analog power source * Ground level input pin for the A-D converter * Apply the same voltage as for the VSS pin to the AVSS pin. Note: This pin is dedicated to the 44P6N-A package products in the 7481 Group. Input * Reference voltage input pin for A-D converter * Apply the following voltage to the VREF pin: 2 V to VCC V when VCC = 2.7 V to 4.0 V, or 0.5 VCC ( 2) to VCC V when VCC = 4.0 V to 5.5 V. Note: When not using A-D converter, connect VREF pin to VCC. * Reset input pin * System Reset: Holding the LOW level for 2 s or more forces CPU into reset state. * I/O pins for clock generator * A ceramic resonator is connected between pins XIN and XOUT. * When an external clock is used, it is input to XIN pin, and leave XOUT pin open. * A feedback resistor is built in between pins XIN and XOUT.
VREF
Reference voltage input
RESET
Reset input
Input
XIN
Clock input
Input
XOUT
Clock output
Output
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HARDWARE
1.5 Pin Descriptions
Table 1.5.2 Pin Descriptions (2) Pin P00-P07 Name I/O port P0 Input/ Output I/O * 8-bit I/O port pins * The output structure is CMOS output. * When an input port is selected, a pull-up transistor can be connectable by the bit. * In input mode, a key-on wake up function is provided. P10-P17 I/O port P1 I/O * 8-bit I/O port pins * The output structure is CMOS output. * When an input port is selected, a pull-up transistor can be connected by the 4 bits. * P12 and P13 serve the alternative functions of the timer output pins T0 and T1. * P14, P15, P16, and P17 serve the alternative functions of the serial I/O pins RxD, TxD, SCLK and SRDY, respectively. P20-P27 Input port P2 Input * 8-bit input port pins * P20-P27 serve the alternative functions of the analog input pins IN0-IN7. Note: The 7480 Group has only four pins of P20-P23 (IN0-IN3). P30-P33 Input port P3 Input * 4-bit input port pins * P30 and P31 serve the alternative functions of the external interrupt input pins INT0 and INT1. * 4-bit I/O port pins * The output structure is N-channel open-drain outputs with built-in clamping diodes. * P40 and P41 serve the alternative functions of the timer I/O pins CNTR0 and CNTR1. Note: The 7480 Group has only two pins of P40 and P41. P50-P53 I/O port P5 I/O * 4-bit I/O port pins * The output structure is N-channel open-drain outputs with built-in clamping diodes. Note: The 7480 Group is not provided with port P5. Function
P40-P43
I/O port P4
I/O
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1-12
VCC
17 16
M37480M8/E8-XXXSP/FP, M37480M8T/E8T-XXXSP/FP FUNCTIONAL BLOCK DIAGRAM
VSS
Clock Clock input output XIN XOUT
Reset input RESET
14
15
18
Data bus
HARDWARE
Clock generator
(Note 2) (Note 1)
RAM 448 bytes ROM 16384 bytes Instruction decoder Timer 2 (8) Control signal INT0 Index register X X (8) Index register Y Y (8) Timer X (16) INT1 Timer Y (16) Processor status register PS (8) Stack pointer S (8)
1.6 Functional Block Diagrams
Program counter PCH (8) Timer 1 (8)
Program counter PCL (8)
Instruction register (8)
1.6 Functional Block Diagrams
Figure 1.6.1 M37480Mx/E8-XXXSP/FP and M37480MxT/E8T-XXXSP/FP Functional Block Diagram
A-D converter CNTR1 INT1 INT0
4
Figures 1.6.1, 1.6.2 and 1.6.3 show the functional block diagrams of the 7480 Group and 7481 Group.
7480 Group and 7481 Group User's Manual
Serial I/O (8) P3 (4) P2 (4) P1 (8)
22 21 20 19 13 9 10 11 12 12345 67 8
8-bit arithmetic and logical unit
Accumulator A (8)
CNTR0
P4 (2)
P0 (8)
24 23
32 31 30 29 28 27 26 25
I/O port P4
VREF Input port P3 Reference voltage input
Input port P2
I/O port P1
I/O port P0
Notes 1: 8192 bytes for the M37480M4-XXXSP/FP, M37480M4T-XXXSP/FP and 4096 bytes for the M37480M2T-XXXSP/FP 2:256 bytes for the M37480M4-XXXSP/FP, M37480M4T-XXXSP/FP and 128 bytes for the M37480M2T-XXXSP/FP
M37481M8/E8-XXXSP, M37481M8T/E8T-XXXSP, M37481E8SS FUNCTIONAL BLOCK DIAGRAM
Reset input RESET VCC VSS
21 22 25
Clock Clock input output XIN XOUT
19
20
Clock generator
Data bus
(Note 2)
(Note 1)
RAM 448 bytes ROM 16384 bytes Instruction decoder Timer 2 (8) Control signal INT0 Index register X X (8) Index register Y Y (8) Timer X (16) INT1 Timer Y (16) Processor status register PS (8) Stack pointer S (8)
Program counter PCH (8) Program counter PCL (8) Timer 1 (8)
Instruction register (8)
Figure 1.6.2 M37481Mx/E8-XXXSP, M37481MxT/E8T-XXXSP and M37481E8SS Functional Block Diagram
7480 Group and 7481 Group User's Manual
A-D converter CNTR0 INT1 INT0
8
8-bit Accumulator arithmetic A (8) and logical unit
Serial I/O (8)
CNTR1
P5 (4) P3 (4)
P4 (4)
P2 (8)
P1 (8)
P0 (8)
1 42 24 23 29 28 27 26
33 32 31 30
18
10 11 12 13 14 15 16 17
23456 78 9
41 40 39 38 37 36 35 34
I/O port P5
I/O port P4
VREF Input port P3 Reference voltage input
Input port P2
I/O port P1
I/O port P0
HARDWARE
1.6 Functional Block Diagrams
Notes 1: 8192 bytes for the M37481M4-XXXSP, M37481M4T-XXXSP and 4096 bytes for the M37481M2T-XXXSP 2: 256 bytes for the M37481M4-XXXSP, M37481M4T-XXXSP and 128 bytes for the M37481M2T-XXXSP
1-13
1-14
Reset input RESET VCC VSS AVSS
16 17 39 18 21 Data bus (Note 2) (Note 1)
M37481M8/E8-XXXFP, M37481M8T/E8T-XXXFP FUNCTIONAL BLOCK DIAGRAM
Clock Clock input output XIN XOUT
14
15
HARDWARE
Clock generator
RAM 448 bytes ROM 16384 bytes Instruction decoder Timer 2 (8)
Program counter PCH (8) Program counter PCL (8) Timer 1 (8)
Instruction register (8)
1.6 Functional Block Diagrams
Control signal INT0 Index register X X (8) Index register Y Y (8) Timer X (16) INT1 Timer Y (16) Processor status register PS (8) Stack pointer S (8)
Figure 1.6.3 M37481Mx/E8-XXXFP, M37481MxT/E8T-XXXFP Functional Block Diagram
7480 Group and 7481 Group User's Manual
A-D converter CNTR0 INT1 INT0
8
8-bit arithmetic and logical unit
Accumulator A (8)
Serial I/O (8)
CNTR1
P5 (4) P3 (4)
P4 (4)
P2 (8)
P1 (8)
P0 (8)
40 38 20 19
29 28 27 26
25 24 23 22
13
5 6 7 8 9 10 11 12
41 42 43 44 1 2 3 4
37 36 35 34 33 32 31 30
I/O port P5
I/O port P4
VREF Input port P3 Reference voltage input
Input port P2
I/O port P1
I/O port P0
Notes 1: 8192 bytes for the M37481M4-XXXFP, M37481M4T-XXXFP and 4096 bytes for the M37481M2T-XXXFP 2:256 bytes for the M37481M4-XXXFP, M37481M4T-XXXFP and 128 bytes for the M37481M2T-XXXFP
HARDWARE
1.7 Central Processing Unit (CPU)
1.7 Central Processing Unit (CPU)
The 7480 Group and 7481 Group have the CPU common to the 740 family. For the description of the instructions, refer to the following: * Section 3.6 Machine Instructions * 740 FAMILY CPU CORE BASIC FUNCTIONS: ADDRESSING MODE in data book SINGLE CHIP 8-BIT MICROCOMPUTERS * SERIES 740 USER'S MANUAL The instructions which characterize the group are as follows: 1. FST and SLW instructions are excluded. 2. MUL and DIV instructions are available. 3. WIT instruction is available (Note). 4. STP instruction is available (Note). Note: For the above instructions, refer to Section 1.19 Power Saving Function. The CPU has the six registers (CPU internal registers). Figure 1.7.1 shows the CPU internal registers.
7
0
A
7 0
Accumulator
X
7 0
Index register X
Y
7 0
Index register Y
S
15 8 7 0
Stack pointer
PCH
7
PCL
0
Program counter
NVTBDI ZC
Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag
Figure 1.7.1 CPU Internal Registers
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HARDWARE
1.7 Central Processing Unit (CPU)
States of the CPU internal registers immediately after system is released from reset are as follows: * The interrupt disable flag (I) of the processor status register (PS) is set to `1'. * The high-order 8 bits (PCH) of the program counter contain the contents of address `FFFF16', and the loworder 8 bits (PCL) contain the contents of address `FFFE16'. Since the contents of the CPU internal registers not mentioned above are undefined immediately after system is released from reset, it is necessary to initialize these registers by software. 1.7.1 Accumulator (A) The accumulator is an 8-bit register. Data manipulations, such as arithmetic or logical operation and transfers, are performed using this register. 1.7.2 Index Register X (X) Index register X is an 8-bit register that performs addressing in the index addressing mode. 1.7.3 Index Register Y (Y) Index register Y is an 8-bit register that performs addressing for certain instructions in the index addressing mode. 1.7.4 Stack Pointer (S) The stack pointer is an 8-bit register. It indicates the start address of the stack area where the contents of registers pushed at subroutine call or interrupt are stored. The low-order 8 bits in the stack are addressed by the stack pointer, and the high-order 8 bits are addressed by the content of the stack page selection bit. When this bit is `0', the high-order 8 bits indicate `0016', and when `1', they indicate `0116'. For the 7480 Group and 7481 Group, the stack page selection bit is assigned to bit 2 of the CPU mode register (address 00FB16). Set this bit to `1' if necessary, because it is cleared to `0' at reset. Note: In the 7480 Group and 7481 Group, however, the product with RAM whose memory size is 192 bytes or less does not have RAM on 1 page. Therefore, clear this bit to `0'. Figure 1.7.2 shows the operation for pushing onto and pulling from the stack. Push the contents of necessary registers other than those described here onto stack by software. Table 1.7.1 lists the push and pull instructions for the accumulator and the processor status register. Initialize the stack pointer by software because it is undefined immediately after system is released from reset. Table 1.7.1 Push and Pull Instructions for Accumulator and Processor Status Register Push Instructions Pull Instructions Accumulator PHA PLA Processor Status Register PHP PLP
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HARDWARE
1.7 Central Processing Unit (CPU)
Routine being executed
*
*
*
*
*
*
*
When an interrupt is accepted Interrupt request (Note) M(S)(PCH) (S)(S) - 1
* * * * * * *
M(S)(PCL) (S)(S) - 1
Push the return address onto stack
When a subroutine is called
Execute JSR
M(S)(PS) (S)(S) - 1
Push the contents of processor status register onto stack
M(S)(PCH)
Push the return address onto stack
Interrupt service routine
* *
(S)(S) - 1 M(S)(PCL) (S)(S) - 1
* * * * * * *
I flag: `0' `1' Fetch the jump vector
Execute RTI Subroutine (S)(S) + 1
*
*
*
(PS)M(S) (S)(S) + 1 (PCL)M(S) (S)(S) + 1
Pull the contents of processor status register from stack
*
*
*
Execute RTS (S)(S) + 1
Pull the return address from stack
Pull the return address from stack
(PCH)M(S)
(PCL)M(S) (S)(S) + 1 (PCH)M(S) : Operation performed by software : Operation automatically performed by hardware
Note: Condition for acceptance of an interrupt *
*
*
Interrupt disable flag is `0' (enabled state) Interrupt enable bit is `1' (enabled state)
Figure 1.7.2 Operation for Pushing onto and Pulling from Stack
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HARDWARE
1.7 Central Processing Unit (CPU)
1.7.5 Program Counter (PC) The program counter is a 16-bit counter consisting of the high-order 8 bits (PCH) and the low-order 8 bits (PCL). The program counter indicates the address of the program memory to be next fetched. At reset, the high-order 8 bits (PCH) of the program counter contain the contents of address `FFFF16', and the low-order 8 bits (PCL) contain the contents of address `FFFE16'. 1.7.6 Processor Status Register (PS) The processor status register is an 8-bit register. This register consists of 5 flags which hold the states immediately after arithmetic or logical operation, and 3 flags which determine the CPU operation. C, Z, V, and N flags are used to test the branch instructions. However, Z, V, and N flags are invalid in the decimal mode. Each flag of the processor status register is described below. Also, Table 1.7.2 lists the instructions that set these flags to `1' or `0'. (1) Carry Flag C (bit 0) This flag holds a carry or a borrow from the arithmetic logic unit after following an arithmetic or logical operation. Also, the shift and rotate instructions can affect the content of this flag. The Carry flag is set to `1' by using the SEC instruction and cleared to `0' by using the CLC instruction. (2) Zero Flag Z (bit 1) This flag is `1' when the result of an arithmetic, logical or transfer operation is `0', otherwise it is `0'. The Zero flag is invalid in the decimal mode. There is no instruction that can affect the content of this flag. (3) Interrupt Disable Flag I (bit 2) This flag disables all interrupts except the BRK instruction interrupt. When it is set to `1', interrupt is disabled. When an interrupt is accepted, the flag automatically goes to `1'. This flag is set to `1' by using the SEI instruction and cleared to `0' by using the CLI instruction. Note: This flag is set to `1' (interrupt disabled) at reset. (4) Decimal Mode Flag D (bit 3) This flag determines whether addition and subtraction are performed in the binary or decimal mode. When this flag is `0', ordinary binary operation is performed; On the other hand, when it is `1', an 8bit word is handled as a decimal number of two digits. Decimal adjust is automatically performed in the decimal operation. However, the decimal operation can be performed only at the ADC and SBC instructions. This flag is set to `1' by using the SED instruction and cleared to `0' by using the CLD instruction. Note: This flag is undefined at reset; then it is necessary to initialize this flag because it directly affects the result of arithmetic operation.
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HARDWARE
1.7 Central Processing Unit (CPU)
(5) Break Flag B (bit 4) This flag recognizes whether an interrupt occurs by using the BRK instruction. The contents of processor status register are pushed onto the stack when the following occurs; * the contents of this flag is set to `1' when an interrupt occurs by using the BRK instruction, or * this flag is set to `0' by the all other interrupts. There is no instruction that can affect the content of this flag. (6) Index X Mode Flag T (bit 5) When this flag is `0', operation is performed between the accumulator and memories. When this flag is `1', operation is directly done between memories without using the accumulator. This flag is set to `1' by using the SET instruction and cleared to `0' by using the CLT instruction. Note: This flag is undefined at reset; it is therefore necessary to initialize this flag because it directly affects the result of operation. (7) Overflow Flag V (bit 6) This flag is used in adding or subtracting an 8-bit word as signed binary digits. When the result of addition or subtraction exceeds the range of +127 to -128, this flag is set to `1'. When the BIT instruction is executed, the content of bit 6 of the activated memory is written to the flag. This flag is cleared to `0' by using the CLV instruction. However, there is no instruction that can set this flag to `1'. In the decimal mode, this flag is invalid. (8) Negative Flag N (bit 7) When the result of arithmetic, logical or transfer operation is negative (bit 7 is `1'), this flag is set to `1'. When the BIT instruction is executed, the content of bit 7 of the activated memory is written to the flag. There is no instruction that can directly affect the content of this flag. In the decimal mode, this flag is invalid. Table 1.7.2 Instructions to Set Flags of Processor Status Register to `1' or `0' C Flag Z Flag I Flag D Flag B Flag T Flag Instructions to Set SEC - SEI SED - SET Flags to `1' Instructions to Set Flags to `0' CLC - CLI CLD - CLT
V Flag - CLV
N Flag - -
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HARDWARE
1.8 Access Area
1.8 Access Area
For the 7480 Group and 7481 Group, all ROM, RAM and I/O and various control registers are located in the same access area. Therefore, data transfer, arithmetic and logical operations can be accomplished by the same instructions without identifying between memory and I/O interface. The program counter consists of 16 bits and can access the 64K-byte area of addresses `000016' through `FFFF16'. The area of the least significant 256 bytes (addresses `000016' through `00FF16') is called the `zero page'. Frequently accessed memory such as an internal RAM, I/O ports, timers, etc are located in this area. Furthermore, the area of the most significant 256 bytes (addresses `FF0016' through `FFFF16') is called the `special page'. An internal ROM and interrupt vectors are located in this area. Both the zero page and the special page can be accessed with two bytes, using the specific mode for each page. Figure 1.8.1 shows the outline of the access area.
000016
RAM
00C016 00FF16
Zero page
SFR area
RAM
FF0016
ROM
Special page
FFFF16
Interrupt vector area
Figure 1.8.1 Access Area
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HARDWARE
1.8 Access Area
1.8.1 Zero Page (Addresses `000016' through `00FF16') The area of 256 bytes from addresses `000016' through `00FF16' is called the zero page. The internal RAM and the special function registers (SFR) are located in this area. The addressing modes shown in Table 1.8.1 are used to specify memory or registers in this area. In the mode listed, the zero page addressing mode can be used to access this area by shorter instruction cycles. 1.8.2 Special Page (Addresses `FF0016' through `FFFF16') The area of 256 bytes from addresses `FF0016' through `FFFF16' is called the special page. The internal ROM and the interrupt vector area are located in this area. The addressing modes shown in Table 1.8.1 are used to specify memory or subroutines in this area. In the mode listed, the special page addressing mode can be used to jump to this area by shorter instruction cycles. Ordinary, frequently used subroutines are located in this area. Table 1.8.1 Addressing Mode Accessible to Each Area Addressing Mode Reference to Zero Page Reference to Special Page Reference to Other Areas (Required Bytes) Zero Page (2) Zero Page Indirect (2) Zero Page X (2) Zero Page Y (2) Zero Page Bit (2) Zero Page Bit Relative (3) Absolute (3) Absolute X (3) Absolute Y (3) Relative (2) Indirect (3) Indirect X (2) Indirect Y (2) Special Page (2) O O O O O O O O O O O O O - - - - - - - O O O O O O O O - - - - - - O O O O O O O -
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HARDWARE
1.9 Memory Maps
1.9 Memory Maps
Figure 1.9.1 shows the memory maps of the 7480 Group and 7481 Group. Memories and I/Os located in the access area are described below. q RAM The internal RAM is located in the area listed in Table 1.9.1. Internal RAM is used for data storage, the stack area used subroutine call or interrupt generation. To prevent the contents of RAM from being destroyed, take the depth of subroutine nesting and the level of interrupt into consideration when using RAM as the stack area. Special Function Registers (SFR) (Addresses `00C016' through `00FF16') Special function registers (SFR) are assigned to addresses `00C016' through `00FF16'. Various control registers for the I/O ports, the timers, the serial I/O, the A-D converter, and the interrupts are located in the SFR area. Figure 1.9.2 shows the memory map of the SFR area. ROM The internal ROM is located in the area listed in Table 1.9.2. Internal ROM is used to store data tables and programs. In the 7480 Group and 7481 Group, addresses `FFE416' through `FFFF16' of the ROM area are assigned to the vector area where the jump addresses after system is released from reset and interrupt generation are stored. Figure 1.9.3 shows the memory map of the interrupt vector area.
q
q
Table 1.9.1 RAM Area Product Range of RAM Area M3748xM2 Addresses `000016' through `007F16' M3748xM4 M3748xM8/E8 Addresses `000016' through `00BF16', Addresses `010016' through `013F16' Addresses `000016' through `00BF16', Addresses `010016' through `01FF16'
RAM Size 128 x 8 bits 256 x 8 bits 448 x 8 bits
Table 1.9.2 ROM Area Product Memory Type M3748xM2 Mask ROM M3748xM4 M3748xM8 M3748xE8 Mask ROM Mask ROM PROM
Range of ROM Area Addresses `F00016' through `FFFF16' Addresses `E00016' through `FFFF16' Addresses `C00016' through `FFFF16'
ROM Size 4K x 8 bits 8K x 8 bits 16K x 8 bits
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HARDWARE
1.9 Memory Maps
M37480M2 M37481M2
000016 007F16 008016 00BF16 00C016 00FF16
M37480M4 M37481M4
000016
M37480M8/E8 M37481M8/E8
000016
RAM (128 bytes)
Not used
RAM (192 bytes)
RAM (192 bytes) Zero page
SFR area
00BF16 00C016 00FF16 010016 013F16
SFR area RAM (64 bytes)
00BF16 00C016 00FF16 010016
SFR area RAM (256 bytes)
01FF16
Not used
Not used
Not used
C00016
E00016
F00016
ROM (4096 bytes)
FF0016 Interrupt vector area FFE416 FFFF16
ROM (8192 bytes)
FF0016 Interrupt vector area FFE416 FFFF16
ROM (16384 bytes) Special page
FF0016 FFE416 FFFF16
Interrupt vector area
Figure 1.9.1 Memory Maps of 7480 Group and 7481 Group
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HARDWARE
1.9 Memory Maps
00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16
Port P0 register (P0) Port P0 direction register (P0D) Port P1 register (P1) Port P1 direction register (P1D) Port P2 register (P2) Port P3 register (P3) Port P4 register (P4) Port P4 direction register (P4D) Port P5 register (P5) Port P5 direction register (P5D)
Port P0 pull-up control register (P0PCON) Port P1 pull-up control register (P1PCON) Port P4P5 input control register (P4P5CON) Edge polarity selection register (EG)
A-D control register (ADCON) A-D conversion register (AD)
STP instruction operation control register (STPCON)
00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 (Note) 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Transmit/receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) Bus collision detection control register (BUSARBCON)
Watchdog timer H (WDTH) Timer X low-order (TXL) Timer X high-order (TXH) Timer Y low-order (TYL) Timer Y high-order (TYH) Timer 1 (T1) Timer 2 (T2) Timer X mode register (TXM) Timer Y mode register (TYM) Timer XY control register (TXYCON) Timer 1 mode register (T1M) Timer 2 mode register (T2M) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Note: These registers are not allocated in the 7480 Group.
Figure 1.9.2 Memory Map of SFR Area
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1.9 Memory Maps
FFE416 FFE516 FFE616 FFE716 FFE816 FFE916 FFEA16 FFEB16 FFEC16 FFED16 FFEE16 FFEF16 FFF016 FFF116 FFF216 FFF316 FFF416 FFF516 FFF616 FFF716 FFF816 FFF916 FFFA16 FFFB16 FFFC16 FFFD16 FFFE16 FFFF16
BRK instruction interrupt A-D conversion completion interrupt Bus arbitration interrupt Serial I/O transmit interrupt Serial I/O receive interrupt Timer 2 interrupt Timer 1 interrupt Timer Y interrupt Timer X interrupt CNTR1 interrupt CNTR0 interrupt INT1 interrupt or key-on wakeup interrupt INT0 interrupt Reset
Note: Refer to Section 1.11 Interrupts for each interrupt overview.
Figure 1.9.3 Memory Map of Interrupt Vector Area
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HARDWARE
1.10 Input/Output Pins
1.10 Input/Output Pins
The Input/Output (I/O) pins of the 7480 Group and 7481 Group are classified as follows: * I/O port pins (P00-P07, P10-P17, P40-P43, and P50-P53) * Input port pins (P20-P27 and P30-P33) * Reset input pin (RESET) * Clock input and output pins (XIN and XOUT) * A-D conversion reference voltage input pin (VREF) * Power source pins (VCC, VSS, and AVSS) Notes 1: The 7480 Group does not have port pins P24-P27, P42, P43, and P50-P53. 2: The AVSS pin is dedicated to the 44P6N-A package products in the 7481 Group. For the functions of each pin, refer to Section 1.5 Pin Descriptions. 1.10.1 Block Diagrams Figures 1.10.1, 1.10.2, and 1.10.3 show the block diagrams of the I/O and input port pins.
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HARDWARE
1.10 Input/Output Pins
q Port P0
Pull-up control register
Tr1 Direction register Data bus Port latch
Port pins P0i (i = 0 to 7)
Interrupt control circuit
Tr1: Pull-up transistor
q Ports P10-P13
Data bus
Pull-up control register
Timer 2 operation mode bit Direction register Data bus Port latch
Tr2
Port P13 pin
T1 Timer 1 operation mode bit Direction register Data bus Port latch Tr3
Port P12 pin
T0 Tr4 Direction register Data bus Port latch
Port P11 pin
Tr5 Direction register Data bus Port latch
Port P10 pin
Tr2 to Tr5: Pull-up transistor
Figure 1.10.1 Block Diagrams of Port Pins P0i and P10-P13
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HARDWARE
1.10 Input/Output Pins
q Ports P14-P17
Serial I/O enable bit Serial I/O mode selection bit SRDY output enable bit Tr6 Direction register Data bus Port latch
Port P17 pin
SRDY
Serial I/O synchronous clock selection bit Serial I/O enable bit Serial I/O mode selection bit Serial I/O enable bit Tr7 Direction register Data bus Port latch
Port P16 pin
SCLK output Serial I/O enable bit Transmit enable bit
SCLK input
Tr8 Direction register Data bus Port latch
Port P15 pin
TxD Serial I/O enable bit Receive enable bit Tr9 Direction register Data bus Port latch
Port P14 pin
RxD Pull-up control register
Data bus
Tr6 to Tr9: Pull-up transistor
Figure 1.10.2 Block Diagram of Port Pins P14-P17
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HARDWARE
1.10 Input/Output Pins
q Port P2
Data bus
Port pins P2i (i = 0 to 7 for 7481 Group, i = 0 to 3 for 7480 Group)
Multiplexer
A-D conversion circuit
q Port P3
Data bus INT0, INT1
Port pins P3i (i = 0 to 3)
q Ports P40 and P41
Timer X, Y operating mode bits
`001' `100' `101' `110'
Direction register Data bus Port latch
Port pins P40 and P41
Timer output CNTR0, CNTR1 input
q Ports P42, P43, and P5
Direction register Data bus Port latch
Port pins P42, P43, and P5i (i=0 to 3)
Port P4P5 input control register * For the 7480 Group, set this register to `0016'. * For the 7481 Group, set the bit corresponding to the port set to the input mode to `1'.
Figure 1.10.3 Block Diagrams of Port Pins P2i to P5i
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HARDWARE
1.10 Input/Output Pins
1.10.2 Registers Associated with I/O Pins Figure 1.10.4 shows the memory map of the registers associated with I/O pins.
00C016 Port P0 register (P0) 00C116 Port P0 direction register (P0D) 00C216 Port P1 register (P1) 00C316 Port P1 direction register (P1D) 00C416 Port P2 register (P2) 00C516 00C616 Port P3 register (P3) 00C716 00C816 Port P4 register (P4) 00C916 Port P4 direction register (P4D) 00CA16 Port P5 register (P5) 00CB16 Port P5 direction register (P5D)
(Note)
00D016 Port P0 pull-up control register (P0PCON) 00D116 Port P1 pull-up control register (P1PCON) 00D216 Port P4P5 input control register (P4P5CON)
Note: These registers are not allocated in the 7480 Group.
Figure 1.10.4 Memory Map of Registers Associated with I/O Pins
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(1) Port Pi Registers (i = 0 to 5) Each port register can read the states of the port pins and specify the output levels of them. Pin used for input (Ports P0 to P5) * A read: When reading from port register corresponding to each port, the input value (state of the pin) is read; the contents of port latch is not read. * A write: When writing to port register corresponding to each port, data is written only into the port latch; the state of the pin is unaffected. Pin used for output (Ports P0, P1, P4, and P5) * A read: When reading from port register corresponding to each port, the written value into the port latch is read; the state of the pin is not read. Therefore, even if the output voltage is affected by the external load etc., the last output value can correctly be read. * A write: When writing to port register corresponding to each port, data written into a bit of the port register can be output to the external circuit through the output transistor. Note: The 7480 Group does not have port P5 and, consequently, is not provided with the port P5 register. Figure 1.10.5 shows the port Pi registers (i = 0 to 5).
Port Pi (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi, i=0 to 5) [Addresses 00C016,00C216,00C416,00C616,00C816,00CA16]
b 0 1 2 3 4 5 6 7
Function When used as input ports (Ports P0 to P5) * At reading, input level of pin is read. * At writing, writing to port latch is performed and the pin state is not affected. When used as output ports (Ports P0, P1, P4, P5) * At reading, the last written value into the port latch is read. * At writing, the written value is output externally through a transistor.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R O O O O O O O O
W O O O O O O O O
Note: * In the 7480 Group, port P2 has only bits 0 to 3. The other bits are not implemented. (undefined at reading). * Port P3 has only bits 0 to 3. The other bits are not implemented (`0' at reading). * In the 7480 Group, port P4 has only bits 0 and 1. In the 7481 Group, port P4 has only bits 0 to 3. The other bits are not implemented. (bits 4 to 7: `0' at reading, bits 2 and 3 in the 7480 Group: undefined). * The 7480 Group does not have port P5. In the 7481 Group, port P5 has only bits 0 to 3. The other bits are not implemented. (`0' at reading).
Figure 1.10.5 Port Pi Registers (i = 0 to 5)
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(2) Port Pi Direction Registers (i = 0, 1, 4, 5) These registers switch the input and output of the programmable I/O port pins P00-P07, P10-P17, P40-P43, and P50-P53. Note: The 7480 Group does not have port P5 and, consequently, is not provided with the port P5 direction register. Figure 1.10.6 shows the port Pi direction registers (i = 0, 1, 4, 5).
Port Pi direction register (i=0,1,4,5)
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD, i=0,1,4,5) [Addresses 00C116,00C316,00C916,00CB16] b 0 1 2 3 4 5 6 7 Name Port Pi direction register (Note) At reset 0 0 0 0 0 0 0 0 R O W O
Function 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode
O O O O O O O
O O O O O O O
Note: * In the 7480 Group, port P4 direction register has only bits 0 and 1. In the 7481 Group, port P4 direction register has only bits 0 to 3. The other bits are not implemented (bits 4 to 7: `0' at reading, bits 2 and 3 in the 7480 Group: undefined). * The 7480 Group does not have port P5 direction register. In the 7481 Group, port P5 has only bits 0 to 3. The other bits are not implemented (`0' at reading).
Figure 1.10.6 Port Pi Direction Registers (i = 0, 1, 4, 5)
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(3) Port Pi Pull-up Control Registers (i = 0, 1) When any pin of ports P0 and P1 is used for input, the corresponding bit of the port Pi pull-up control register controls the pull-up of the pin. Pull-up control is performed by the ON/OFF switch of a pull-up transistor. Pull-up control is valid only when the pin is used for input and invalid when used for output or serial I/O. Note: Port P1 controls the pull-up of high- or low-order four bits at one time. Even if only port P10 pin is pulled high, for example, port pins P11-P13 are also pulled high simultaneously. Figures 1.10.7 and 1.10.8 show the port P0 and the port P1 pull-up control registers.
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0 Port P0 pull-up control register (P0PCON) [Address 00D016]
b 0 1 2 3 4 5 6 7
Name P00 pull-up control bit P01 pull-up control bit P02 pull-up control bit P03 pull-up control bit P04 pull-up control bit P05 pull-up control bit P06 pull-up control bit P07 pull-up control bit
Function 0 : P00 No pull-up 1 : P00 Pull-up 0 : P01 No pull-up 1 : P01 Pull-up 0 : P02 No pull-up 1 : P02 Pull-up 0 : P03 No pull-up 1 : P03 Pull-up 0 : P04 No pull-up 1 : P04 Pull-up 0 : P05 No pull-up 1 : P05 Pull-up 0 : P06 No pull-up 1 : P06 Pull-up 0 : P07 No pull-up 1 : P07 Pull-up
At reset 0 0 0 0 0 0 0 0
R O O O O
W O O O O
O O O O
O O O O
Note: Pull-up control is valid when the corresponding port is set to the input mode.
Figure 1.10.7 Port P0 Pull-up Control Register
Port P1 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0 Port P1 pull-up control register (P1PCON) [Address 00D116]
b 0 1 2 3 4 5 6 7
Name P13-P10 pull-up control bit P17-P14 pull-up control bit
Function 0 : P10-P13 No pull-up 1 : P10-P13 Pull-up 0 : P14-P17 No pull-up 1 : P14-P17 Pull-up
At reset 0 0
Undefined Undefined Undefined Undefined Undefined Undefined
R O O
Undefined Undefined Undefined Undefined Undefined Undefined
W O O x x x x x x
Not implemented. Writing to these bits is disabled. These bits are undefined at reading.
Note: Pull-up control is valid only when the corresponding port is set to the input mode. When port pins P15-P17 are used as serial I/O pins, pull-up control of the corresponding port pins is invalid.
Figure 1.10.8 Port P1 Pull-up Control Register
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(4) Port P4P5 Input Control Register When port pins P42, P43, and P50-P53 of the 7481 Group are used as input ports, set the corresponding bits of the port P4P5 input control register to `1'. Note: The 7480 Group does not have port pins P42, P43, and P50-P53; therefore, set the port P4P5 input control register to `0016'. Figure 1.10.9 shows the port P4P5 input control register.
Port P4P5 input control register
b7 b6 b5 b4 b3 b2 b1 b0
000000
Port P4P5 input control register (P4P5CON) [Address 00D216]
b 0 1 2 3 4 5 6 7
Name P42, P43 input control bit P5 input control bit
Function When the P42, P43 are used as the input port, set this bit to `1'. When the P5 is used as the input port, set this bit to `1'.
At reset 0 0 0 0 0 0 0 0
R O
W O
O 0 0 0 0 0 0
O x x x x x x
Not implemented. Writing to these bits is disabled. These bits are `0' at reading.
Note: 7480 Group does not have port pins P42, P43 and P5, so set this register to `0016'.
Figure 1.10.9 Port P4P5 Input Control Register
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1.10.3 I/O Ports (1) Writes to and Reads from I/O Port Pins Pin used for input (Ports P0 to P5) * A read: When reading from port register corresponding to each port, the input value (state of the pin) is read; the contents of port latch is not read. * A write: When writing to port register corresponding to each port, data is written only into the port latch; the state of the pin is unaffected. Pin used for output (Ports P0, P1, P4, and P5) * A read: When reading from port register corresponding to each port, the written value into the port latch is read; the state of the pin is not read. Therefore, even if the output voltage is affected by the external load etc., the last output value can correctly be read. * A write: When writing to port register corresponding to each port, data written into a bit of the port register can be output to the external circuit through the output transistor. Figure 1.10.10 shows a write and a read of an I/O port pin.
Pins used for input
* By reading from port register, input level of pin can be read. * By writing to port register, writing to port latch is performed.
Pins used for output
* By reading from port register, port latch can be read. * By writing to port register, output value can be set.
`H' level output Port direction register (`0') (Note) Port direction register (`1')
Port register (When Writing)
Port register (When Writing) Port register (When Reading) `L' level output
Port register (When Reading)
Note: The P-channel transistor and the N-channel transistor are in a cut-off state.
Figure 1.10.10 Write and Read of I/O Port Pin
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(2) Switching of Programmable I/O Port Pins Any pin of the programmable I/O ports P0, P1, P4, and P5 can be switched from input to output or from output to input with the corresponding bit of their port direction registers. * The pin is set to the input mode when the corresponding bit is `0'. * The pin is set to the output mode when the corresponding bit is `1'. Notes 1: In the 7480 Group, port P4 contains pins P40 and P41 only, while in the 7481 Group, port P4 contains pins P40-P43. In addition, the 7480 Group does not have port P5, while the 7481 Group has port P5, consisting of P50-P53. 2: After system is released from reset, all of the programmable I/O port pins are set to the input mode. (The corresponding direction registers are cleared to all `0'.) 3: When any of port pins P42, P43, and P50-P53 is used as an input port pin, clear the corresponding bit of the port P4 and P5 direction registers to `0'. In addition, set the corresponding input control bit of the port P4P5 input control register to `1'. The 7480 Group does not have port pins P42, P43, and P50-P53; therefore, set the port P4P5 input control register to `0016'. (3) Pull-up Control When any pin of ports P0 and P1 is used as an input port pin, its pull-up can be controlled with the corresponding bit of the port P0 and P1 pull-up control registers. * A port pin is not pulled high when the corresponding bit is `0'. * A port pin is pulled high when the corresponding bit is `1'. Pull-up control is performed by the ON/OFF switch of a pull-up transistor. Pull-up control is valid only when the pin is used for input and invalid when used for output or serial I/O. Note: Port P0 controls the pull-up by the bit at one time. Port P1, however, controls the pull-up of the high- or low-order four bits at one time. Even if only port P10 pin is pulled high, for example, port pins P11-P13 are also pulled high simultaneously.
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(4) Level Shift Ports Every pin of ports P4 and P5 acts as an N-channel open-drain output and is provided with a builtin clamping diode. When voltage VI is applied to a pin through a resistor as shown in Figure 1.10.11, and the current I flowing in a clamping diode is 1 mA or less, the condition VI > VCC can be maintained.
VI
I
Port P4 Port P5
7480 Group 7481 Group
Figure 1.10.11 Port P4 and P5 Circuit Notes 1: In the 7480 Group, port P4 contains pins P40 and P41 only, while in the 7481 Group, port P4 contains pins P40-P43. In addition, the 7480 Group does not have port P5, while the 7481 Group has port P5, consisting of P50-P53. 2: Total Input Current It is required to keep the current flowing to the clamping diodes of port P4 or P5 equal to or less than 1.0 mA a pin; a current which is too large for the microcomputer can handle will raise the voltage on the power source pin. To protect the device, use an appropriate power circuit to stabilize the power source voltage within specifications. 3: Maximum Input Voltage If the input signal voltage to port P4 or P5 exceeds VCC + 0.3 V, a delay time of 2 s/V or more is necessary immediately after the input waveform exceeds the above voltage. Delay time can be calculated by the following expression in CR integrating circuits. dt = t 1 dv 0.6 x VIN2 2 x 10- 6 [s/V]
1: Delay time t = C x R 2: VIN = maximum amplitude difference of input voltage 4: Clamping diodes used in the 7480 Group and 7481 Group differ from the normal switching diodes. These clamping diodes are used only for the DC signal level shifts. Therefore, sudden stress, such as a rush current must not be applied directly to the diodes. (5) Ports with Built-in Schmidt Trigger Circuits A Schmidt trigger circuit is built into every pin of ports P3, P4, and P5 of the 7481 Group. When any of port pins P42, P43, and P50-P53 is used as an input port pin, clear the corresponding bit of the port P4 and P5 direction registers to `0'. In addition, set the corresponding input control bit of the port P4P5 input control register to `1'. Note: The 7480 Group does not have pins P42, P43, and P50-P53; therefore, set the port P4P5 input control register to `0016'.
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1.10.4 Termination of Unused Pins Table 1.10.1 lists the termination of unused pins. Table 1.10.1 Termination of Unused Pins Port P0 P10-P13 P15, P17 P14, P16 P2 (Note 8) P3 P4, P5 (Note 8) AVSS (Note 9) VREF XOUT O (Note 5) O (Note 2) x O (Note 5) x x O O (Note 3) O (Note 6) O (Note 6) O (Note 3) x x x O (Note 4) O (Note 6) O (Note 6) O (Note 7) x x x x x O (Note 6) O (Note 6) O (Note 6) O (Note 6) x x O x x O x x Pull-up to VCC through a resistor (Note 1) O (Note 3) Termination Pull-down to VSS through Connect to Connect to VSS a resistor (Note 1) VCC O (Note 4) x x
Open
O (Note 2)
Notes 1: Do not connect several pins of programmable I/O ports together to VCC or VSS through a resistor. 2: Every pin that is allowed to be open when unused has a special circuit structure which prevents currents from flowing into the circuit unless the input to read signal is performed internally, even if an intermediate level input is applied to the pin. 3: When these pins are pulled high, set the corresponding bits of port direction registers, port registers and port P4P5 input control register so that each pin is in the input mode or output is HIGH. 4: When these pins are pulled low, set the corresponding bits of port direction registers, pull-up control registers, port registers so that each pin can be set to the input mode without pull-up transistor or in the output is LOW. 5: Set these pins to the output mode and keep them open. However, these I/O pins retain the input mode until the pins are switched to the output mode by software after the microcomputer is released from reset. Therefore, the power source current may increase depending on the input level of each pin. Since their port direction registers might be switched into the input mode by program runaway or noise, periodically set the port direction registers to the output mode by software. 6: A short wire can be used to directly connect any unused pin to the VCC or VSS pin without a resistor, but a long wire must connect it through a resistor. Since the P33 pin of the built-in PROM version has the alternative function of the VPP pin, connect the P33 pin to VCC or VSS with the shortest wire through a resistor (about 5 k), in series. 7: When these pins are pulled low, set the corresponding bits of port direction registers, port registers and port P4P5 input control register so that each pin is in the input mode or output is LOW. 8: The 7480 Group does not have port pins P24-P27, P42, P43, and P50-P53. 9: The AVSS pin is dedicated to the 44P6N-A package products in the 7481 Group.
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1.10.5 Notes on Usage Pay attention to the following notes when the I/O ports are used. (1) Rewriting to Port Register of I/O Port Rewriting to the port register of an I/O port with a bit manipulation instruction 1 may affect the values of the bits not specified. 1: `Bit manipulation instructions': the CLB and SEB instructions REASON: The bit manipulation instructions are read-modify-write instructions. These instructions read and write data by the byte. Therefore when these instructions are executed for any one bit of the port register of an I/O port, the following processing is performed to all of the bits of the register: * For bits that are set to the input mode, the states of the corresponding pins are read into the CPU, and after the bit manipulation, the bits of the port register are rewritten. * For bits that are set to the output mode, the values of the port latches are read into the CPU, and after the bit manipulation, the bits of the port register are rewritten. Pay attention also to the following: * Even if a port pin set to the output mode is switched to the input mode, output data is retained in the port register. * When the state of a port pin and the content of the corresponding bit of the port register are different, the content of the bit of the port register set to the input mode may be affected even if this bit is not specified by a bit manipulation instruction. (2) Pull-up Control of Ports P0 and P1 When any of pins P15-P17 is used as a serial I/O pin, the pull-up control of the pin is invalid. (The pin cannot be pulled high.) For details, refer to Figure 1.10.2 Block Diagram of Port Pins P14-P17. When any pin of ports P0 and P1 is used as an output port pin, the pull-up control of the pin is invalid. (The pin cannot be pulled high.) For details, refer to Figure 1.10.1 Block Diagrams of Port Pins P0i and P10-P13 and Figure1.10.2 Block Diagram of Port Pins P14-P17. Port P1 controls pull-up the high- or low-order four bits at one time. Even if only port P10 pin is pulled high, for example, port pins P11-P13 are pulled high simultaneously.
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(3) Transition to Standby State (Note) At the transition to the standby state, do not leave the input levels of input port pins and I/O port pins undefined (especially pins P14, P16, P3, P4, and P5). In an N-channel open-drain I/O pin, when the corresponding bit of the port register is `1', its transistor remains in an off state even if the pin is set to output mode with the port direction register. As a result, the pin goes to a high impedance state, causing the level of the pin to be undefined depending on the external circuit. In such a case, a through current flows to the gate of the input stage, so that the power source current may increase. Note: The standby state means the following: The stop mode by an execution of the STP instruction The wait mode by an execution of the WIT instruction. Actual Example Pull a pin high (connect to VCC) or low (connect to VSS) through a resistor. Choose a resistor taking the following into consideration: * External circuit condition * Variation of output levels at normal operation Also, take account of the variation of current when pull-up transistors of ports P0 and P1 are used. (4) Usage of Pins P12, P13, P40, and P41 as Normal Output Pins Pins P12 and P13 have the alternative functions of the 8-bit timer output pins T0 and T1 respectively. Pins P40 and P41 also have the alternative functions of 16-bit timer I/O pins CNTR0 and CNTR1 respectively. When the operating mode bits of the corresponding timer are set to any mode related to output (Note), these pins cannot operate as normal output pins. Refer to Figure 1.10.1 Block Diagrams of Port Pins P0i and P10-P13 and Figure 1.10.3 Block Diagrams of Port Pins P2i to P5i. Note: Modes related to output: For 8-bit timers (timer 1 and timer 2): * Programmable waveform generation mode For 16-bit timers (timer X and timer Y): * Pulse output mode * Programmable waveform generation mode * Programmable one-shot output mode * PWM mode (5) Usage of Port Pins P42, P43, and P50-P53 as Input Ports When any of port pins P42, P43, and P50-P53 of the 7481 Group are used as an input port pin, clear the corresponding bit of the port P4 and P5 direction registers to `0', and set the corresponding input control bit of the port P4P5 input control register to `1'.
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1.11 Interrupts
The interrupt function is used to suspend the routine being executed by any interrupt source and to execute another routine. An interrupt is used in the following cases: * When processing of a higher priority than the routine being executed is requested. * When processing is requested to be performed according to a special timing. Table 1.11.1 lists the interrupt sources available in the 7480 Group and 7481 Group. Table 1.11.1 Interrupt Sources Priority Order 1 2 3 4 5 6 7 8 9 10 11 12 13 Interrupt Source Reset (Note 1) INT0 INT1 Key-on Wakeup CNTR0 CNTR1 Timer X Timer Y Timer 1 Timer 2 Serial I/O Receive Serial I/O Transmit Bus arbitration Vector Address Comments High-order Low-order FFFF16 FFFE16 Non-maskable (Note 2) FFFD16 FFFC16 External interrupt (Polarity programmable) FFFB16 FFF916 FFF716 FFF516 FFF316 FFF116 FFEF16 FFED16 FFEB16 FFE916 FFFA16 FFF816 FFF616 FFF416 FFF216 FFF016 FFEE16 FFEC16 FFEA16 FFE816 External interrupt (Polarity programmable) External interrupt External interrupt (Polarity programmable) External interrupt (Polarity programmable) Internal interrupt Internal interrupt Internal interrupt Internal interrupt Internal interrupt Internal interrupt Internal interrupt
FFE616 Internal interrupt A-D conversion complete FFE716 FFE516 FFE416 Non-maskable software interrupt 14 BRK instruction Notes 1: Reset is included in the above table, as well, because it performs the same operation as interrupts. 2: `Non-maskable interrupt': this is the interrupt not having the corresponding interrupt request bit and interrupt enable bit. This interrupt request is accepted regardless of the state of the interrupt disable flag.
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1.11.1 Block Diagram Figure 1.11.1 shows the block diagram of the interrupt inputs and the key-on wakeup circuit.
P40/CNTR0
`0' `1' CNTR0 edge selection bit
Port P40 data read circuit CNTR0 interrupt request signal
P41/CNTR1
`0' `1' CNTR1 edge selection bit
Port P41 data read circuit CNTR1 interrupt request signal
P30/INT0
`0' `1' INT0 edge selection bit
Port P30 data read circuit INT0 interrupt request signal
P31/INT1
`0' `1' INT1 edge selection bit CPU stop state signal Pull-up control register Port direction register
Port P31 data read circuit
`0'
INT1 interrupt request signal
`1' INT1 source selection bit at STP, WIT
P07
Pull-up control register Port direction register
P01 Port P0 data read circuit
Pull-up control register Port direction register
P00
Figure 1.11.1 Block Diagram of Interrupt Inputs and Key-On Wakeup Circuit
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1.11.2 Registers Associated with Interrupt Control Figure 1.11.2 shows the memory map of the registers associated with interrupt control.
00D416
Edge polarity selection register (EG)
00FC16 00FD16 00FE16 00FF16
Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Figure 1.11.2 Memory Map of Registers Associated with Interrupt Control
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1.11 Interrupts
(1) Edge Polarity Selection Register The edge polarity selection register consists of the bits that select the polarity of the valid edge of the INT and CNTR pins, as well as the bit that selects the valid/invalid of the key-on wakeup. Figure 1.11.3 shows the edge polarity selection register.
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0 Edge polarity selection register (EG) [Address 00D416]
b 0 1 2
Name INT0 edge selection bit INT1 edge selection bit CNTR0 edge selection bit 0 : Falling edge 1 : Rising edge
Function
At reset 0 0 0
R O O O
W O O O
3
CNTR1 edge selection bit
0 : Falling edge 1 : Rising edge 0: In event count mode, rising edge counted. : In pulse output mode, operation started at HIGH level output. : In pulse period measurement mode, a period from falling edge until falling edge measured. : In pulse width measurement mode, HIGH-level period measured. : In programmable one-shot output mode, one-shot HIGH pulse generated after operation started at LOW level output. : Interrupt request is generated by detecting falling edge. 1: In event count mode, falling edge counted. : In pulse output mode, operation started at LOW level output. : In pulse period measurement mode, a period from rising edge until rising edge measured. : In pulse width measurement mode, LOW-level period measured. : In programmable one-shot output mode, one-shot LOW pulse generated after operation started at HIGH level output. : Interrupt request is generated by detecting rising edge.
0
O
O
4 5
Not implemented. Writing to this bit is disabled. This bit is undefined at reading. 0 : P31/INT1 INT1 source selection bit at 1 : P00-P07 LOW level (for key-on wake-up) STP or WIT Not implemented. Writing to these bits are disabled. These bits are undefined at reading.
Undefined
Undefined
x
O
0
O
6 7
Undefined Undefined
Undefined Undefined
x x
Note: When setting bits 0 to 3, the interrupt request bit may be set to `1'. After setting the following, enable the interrupt. Disable interrupts Set the edge polarity selection register Set the interrupt request bit to `0'
Figure 1.11.3 Edge Polarity Selection Register
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(2) Interrupt Request Register 1 and Interrupt Request Register 2 Interrupt request registers 1 and 2 consist of the bits that indicate whether or not there is an interrupt request. Figures 1.11.4 and 1.11.5 show the interrupt request registers 1 and 2.
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16]
b 0 1 2 3 4 5 6 7
Name
Function
At reset 0 0 0 0 0 0 0 0
R O O O O O O O O
W
Timer X interrupt request bit 0 : No interrupt request 1 : Interrupt request Timer Y interrupt request bit 0 : No interrupt request 1 : Interrupt request Timer 1 interrupt request bit 0 : No interrupt request 1 : Interrupt request Timer 2 interrupt request bit 0 : No interrupt request 1 : Interrupt request Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Bus arbitration interrupt request bit A-D conversion completion interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request

: The bit can be set to `0' by software, but cannot be set to `1'.
Figure 1.11.4 Interrupt Request Register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address 00FD16]
b 0 1 2 3 4 5 6 7
Name INT0 interrupt request bit INT1 interrupt request bit
Function 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset 0 0 0 0
Undefined Undefined Undefined Undefined
R O
W
x x x x
O O O
Undefined Undefined Undefined Undefined
CNTR0 interrupt request bit 0 : No interrupt request 1 : Interrupt request CNTR1 interrupt request bit 0 : No interrupt request 1 : Interrupt request Not implemented. Writing to these bits is disabled. These bits are undefined at reading.
: The bit can be set to `0' by software, but cannot be set to `1'.
Figure 1.11.5 Interrupt Request Register 2
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(3) Interrupt Control Register 1 and Interrupt Control Register 2 Interrupt control registers 1 and 2 consist of the bits that control the acceptance of interrupts. Figures 1.11.6 and 1.11.7 show the interrupt control registers 1 and 2.
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16]
b 0 1 2 3 4 5 6 7
Name Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Bus arbitration interrupt enable bit A-D conversion completion interrupt enable bit
Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset 0 0 0 0 0 0 0 0
R O O O O O O O O
W O O O O O O O O
Figure 1.11.6 Interrupt Control Register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address 00FF16]
b 0 1 2 3 4 5 6 7
Name INT0 interrupt enable bit INT1 interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit
Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset 0 0 0 0
Undefined Undefined Undefined Undefined
R O O O O
Undefined Undefined Undefined Undefined
W O O O O
Not implemented. Writing to these bits are disabled. These bits are undefined at reading.
x x x x
Figure 1.11.7 Interrupt Control Register 2
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1.11.3 Interrupt Sources In the 7480 Group and 7481 Group, the interrupt requests can be generated by 14 sources (5 external, 8 internal, and 1 software). The interrupts are vectored interrupts whose priority levels are fixed, and each interrupt has its own priority level. When two or more interrupt requests are generated at the same sampling time, which is a timing to test the generation of interrupt requests, the interrupt with a higher priority is acceptable. For the priority levels of interrupts, refer to Table 1.11.1 Interrupt Sources. Each interrupt source is described below. (1) INT0 and INT1 Interrupts When a rising edge or a falling edge of the input signal to the INT0 or INT1 pin is detected, an interrupt request is generated. The edge polarity to be detected can be selected by the INT0 edge selection bit or the INT1 edge selection bit of the edge polarity selection register. The request bit, the enable bit, and the interrupt vector of the INT1 interrupt have the alternative functions of those of the key-on wakeup interrupt respectively. When the INT1 interrupt is used, clear the INT1 source selection bit at the STP/WIT of the edge polarity selection register to `0'. * State after system is released from reset After system is released from reset, the INT0 edge selection bit, INT1 edge selection bit and the INT1 source selection bit at the STP/WIT of the edge polarity selection register are all cleared to `0'. In such conditions, though an interrupt request is generated by detecting a falling edge of the INT0 or INT1 pin, the interrupt request cannot be accepted because the corresponding interrupt enable bit is `0' and the interrupt disable flag is `1'. Notes 1: The INT0 and INT1 pins have the alternative functions of input port pins P30 and P31, respectively. When these pins are used as input port pins, valid edges can still be detected because the 7480 Group and 7481 Group does not have the function to switch the INT pins to input port pins. Therefore, when these pins are used as input port pins, clear all the corresponding interrupt enable bits to `0' (disabled). 2: Keep the trigger width input to the INT pins 250 ns or more. (2) Key-On Wakeup Interrupt When the INT1 source selection bit at the STP/WIT of the edge polarity selection register is `1' and the LOW level is applied to any pin of port P0 which is used as input in the stop/wait mode at the execution of STP/WIT, a key-on wakeup interrupt request is generated. In other states than the stop/ wait mode, the key-on wakeup interrupt is invalid. The request bit, the enable bit, and the interrupt vector of the key-on wakeup interrupt have the alternative functions of those of the INT1 interrupt respectively. When the key-on wakeup interrupt is used, set the INT1 source selection bit at the STP/WIT of the edge polarity selection register to `1'. Note: When the key-on wakeup interrupt is used, execute the STP/WIT instruction after all inputs to port P0 are held HIGH. If the LOW level is applied to any input pin of port P0, an execution of the STP/WIT instruction generates an interrupt request instantly.
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(3) CNTR0 and CNTR1 Interrupts When a rising edge or a falling edge of the input signal to the CNTR0 or the CNTR1 pin is detected, an interrupt request is generated. The edge polarity to be detected can be selected by the CNTR0 edge selection bit or the CNTR1 edge selection bit of the edge polarity selection register. * State after system is released from reset After system is released from reset, the port pins with the alternative functions of CNTR pins are placed in the input mode, and their edge selection bits are held all `0' also. In such conditions, though an interrupt request is generated by detecting a falling edge of the CNTR0 or CNTR1 pin, the interrupt request cannot be accepted because the corresponding interrupt enable bit is `0' and the interrupt disable flag is `1'. Note: The CNTR0 and CNTR1 pins have the alternative functions of I/O port pins P40 and P41, respectively. When these pins are used as input port pins, valid edges can still be detected because the 7480 Group and 7481 Group does not have the function to switch the CNTR pins to input port pins. Therefore, when these pins are used as input port pins, clear all the corresponding interrupt enable bits to `0' (disabled). (4) Timer X, Timer Y, Timer 1, and Timer 2 Interrupts At an underflow in each timer, the corresponding interrupt request is generated. For timer X and timer Y, refer to Section 1.12 Timer X and Timer Y, and for timer 1 and timer 2, refer to Section 1.13 Timer 1 and Timer 2. (5) Serial I/O Receive Interrupt, Serial I/O Transmit Interrupt, and Bus Arbitration Interrupt * Serial I/O receive interrupt During serial I/O reception, a serial I/O receive interrupt request is generated when the received data stored completely in the receive shift register is transferred to the receive buffer register. * Serial I/O transmit interrupt During serial I/O transmission, a serial I/O transmit interrupt request is generated when the transmit buffer register is emptied or the transmit shift operation is complete. * Bus arbitration interrupt In the bus collision detection enable state during the serial I/O communication, the mismatch of levels between transmitter pin TxD and receiver pin RxD generates a bus arbitration interrupt request. The bus collision detection can be enabled by setting the bus collision detection enable bit of the bus collision detection control register. For serial I/O, refer to Section 1.14 Serial I/O. (6) A-D Conversion Complete Interrupt When A-D conversion is completed, an A-D conversion complete interrupt request is generated. For A-D conversion, refer to Section 1.15 A-D Converter. (7) BRK Instruction Interrupt The BRK instruction interrupt is a non-maskable software interrupt. Program branches to the jump address stored in the vector address when the BRK instruction is executed. For the BRK instruction, refer to the section of the BRK instruction in SERIES 740 USER'S MANUAL.
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1.11.4 Interrupt Sequence Interrupt sequence is described below. Generation of Interrupt Requests When an interrupt request other than the BRK instruction interrupt is generated, the interrupt request bit of the corresponding interrupt request register is set to `1'. At this time, the interrupt request is accepted when both the following conditions are satisfied: * The interrupt enable bit of the corresponding interrupt control register is `1'. * The interrupt disable flag of the processor status register is `0'. When the BRK instruction interrupt request is generated, the break flag of the processor status register is set to `1', causing the interrupt request to be accepted unconditionally. For interrupt sources, refer to Section 1.11.3 Interrupt Sources. Also for interrupt control, refer to Section 1.11.5 Interrupt Control. Acceptance of Interrupt Request When an interrupt request is accepted, the following operations are performed: [1] Upon the completion of the instruction being executed, the processing is temporarily suspended. [2] The contents of the program counter and the processor status register are pushed onto the stack in the following order: High-order 8 bits of the program counter Low-order 8 bits of the program counter Processor status register [3] The jump address (the start address of an interrupt service routine) stored in the vector address of the accepted interrupt is set in the program counter, and the interrupt service routine is executed. At this time, the interrupt disable flag is set to `1', and multiple interrupts are disabled. Also, the corresponding interrupt request bit is cleared to `0' for any interrupt other than the BRK instruction interrupt. [4] When the RTI instruction, which is, the last instruction of the interrupt service routine, is executed, the contents of the program counter and the processor status register pushed onto the stack are pulled to the corresponding register in the following order: Processor status register Low-order 8 bits of program counter High-order 8 bits of program counter [5] The program temporarily suspended by the acceptance of the interrupt request is resumed at the address indicated by the program counter. Note: When the BRK instruction is executed, 2 is added to the contents of program counter, and then the contents of the program counter are pushed onto the stack. As a result, upon return from the BRK instruction interrupt service routine, the one byte subsequent to the BRK instruction is not executed. Therefore, at programming, it is necessary to insert the NOP instruction immediately after the BRK instruction.
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Figure 1.11.8 shows an operation when an interrupt request is accepted.
Routine being executed
: Operation performed by software : Operation automatically performed by hardware
****** Interrupt request is generated
Processing at accepting interrupt
1 M(S)(PCH) (S)(S)-1 3 ****** M(S)(PCL) (S)(S)-1 M(S)(PS) (S)(S)-1 2 Interrupt service routine Contents of processor status register are pushed onto stack Contents of program counter are pushed onto stack
Interrupt disable flag `0'`1' Fetch the jump address stored into vector address
RTI instruction execution (S)(S)+1 (PS)M(S) (S)(S)+1 (PCL)M(S) (S)(S)+1 (PCH)M(S) Contents of program counter are pulled from stack
*
*
*
Contents of processor status register are pulled from stack
1 Immediately after interrupt
2
request is accepted
S PCL PCH
b7
Immediately before interrupt service routine is executed
S PCL PCH XXS-3 Jump address (from vector address)
b7 b0
Note
3
Immediately after system returns from interrupt service routine
S PCL PCH
b7
XXS XXPCL XXPCH
b0
Note
XXS XXPCL XXPCH
b0
Note
PS
0 Interrupt disable flag Break flag
PS
1 Interrupt disable flag Break flag
PS
0 Interrupt disable flag Break flag
Stack area (S)=XXS-3
Stack area
Stack area
Note
0
(S)=XXS
XXS
XXPCL XXPCH
(PS) (PCL) (PCH) (S)=XXS
Note: In the case of the BRK instruction interrupt, b4 of PS is set to `1'.
Figure 1.11.8 Operation When Interrupt Request is Accepted
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Processing Before Interrupt Service Routine When an interrupt request is accepted, the interrupt service routine is started after the following are performed. the instruction being executed at the generation of the interrupt request is completed the pipeline postprocessing the pushing onto the stack, and vector fetch Figure 1.11.9 shows the processing time from the interrupt generation until the execution of an interrupt service routine, and Figure 1.11.10 shows a timing at interrupt acceptance.
Interrupt request is generated
Interrupt service routine starts
Main routine
Waiting time for pipeline postprocessing
Push onto stack Vector fetch
Interrupt service routine
0 to 16 cycles (Note)
2 cycles
5 cycles
7 to 23 cycles (At internal system clock = 4 MHz, 1.75 s to 5.75 s) Note: At the DIV instruction executed.
Figure 1.11.9 Processing Time from Interrupt Generation until Execution of Interrupt Service Routine
Waiting time for pipeline postprocessing
Push onto stack Vector fetch
Interrupt service routine starts
SYNC R/W Address bus Data bus
PC Not used S, SPS PCH S-1, SPS S-2, SPS PCL PS BL AL BH AH AL, AH
SYNC: CPU operation code fetch cycle (This is an internal signal which cannot be examined from the external.) BL, BH: Vector address of each interrupt AL, AH: Jump address of each interrupt SPS: `0016' or `0116' (when the stack page selection bit is `0', SPS is `0016', and when the bit is `1', SPS is `0116')
Figure 1.11.10 Timing at Interrupt Acceptance
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Return from Stop/Wait Mode When an interrupt request is accepted in the stop/wait mode, the CPU terminates these modes and returns to the normal mode. Table 1.11.2 lists the interrupt sources available for CPU's return from the stop/wait mode. Table 1.11.2 Interrupt Sources Available for CPU's Return from Stop/Wait Mode (O:Available, x:Not available) Return from Wait Mode Interrupt Source Return from Stop Mode O Reset (Note 1) O INT0 INT1 Key-on Wakeup CNTR0 CNTR1 Timer X Timer Y Timer 1 Timer 2 Serial I/O Receive Serial I/O Transmit Bus Arbitration A-D Conversion Complete BRK Instruction O O O O O O (Note 2) O (Note 2) x x O (Note 3) O (Note 3) O (Note 3) x x O O O O O O O O O O O O O x
Notes 1: Reset is included in the above table, as well, because it performs the same operation as interrupts. 2: Available in the event count mode only. 3: Available only when the external clock input (or the clock divided by 16) is used as the synchronous clock. For details, refer to Section 1.19 Power Saving Function.
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1.11.5 Interrupt Control Figure 1.11.11 shows an interrupt control diagram.
Interrupt request bit Interrupt enable bit Interrupt acceptance Interrupt disable flag BRK instruction Reset
Figure 1.11.11 Interrupt Control Diagram Only when all of the following conditions are satisfied, interrupts other than the BRK instruction interrupt are accepted: * Corresponding interrupt request bit is `1' (interrupt requested). * Corresponding interrupt enable bit is `1' (interrupt enabled). * Interrupt disable flag is `0' (interrupt enabled). The priority level of each interrupt is specified by hardware. However, processing of various priorities can be performed under software control by using the above bits and flag. For the interrupt priority levels, refer to Table 1.11.1 Interrupt Sources. Interrupt Request Bits The interrupt request bits indicate whether or not there are interrupt requests. When an interrupt request is generated, an interrupt request bit is set to `1' and informs the external that the interrupt request is generated. After the interrupt is accepted, the interrupt request bit is automatically cleared to `0'. The interrupt request bits can be cleared to `0' by software, but they cannot be set to `1'. Interrupt Enable Bits The interrupt enable bits control the acceptance of interrupt requests as follows: * When an interrupt enable bit is `0', the acceptance of the corresponding interrupt request is disabled. * When an interrupt enable bit is `1', the acceptance of the corresponding interrupt request is enabled. Interrupt Disable Flag This flag is located in the processor status register. The flag controls the acceptance of the interrupt requests other than the BRK instruction interrupt as follows: * When the interrupt disable flag is `0', the acceptance of interrupt request is enabled. * When the interrupt disable flag is `1', the acceptance of interrupt request is disabled. When the program branches to the interrupt service routine, this flag is automatically set to `1' and disables multiple interrupts. When multiple interrupts are used, clear this flag to `0' at the start of the interrupt service routine.
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1.11.6 Setting of Interrupts Figures 1.11.12 and 1.11.13 show the setting of interrupts.
Procedure 1 Setting interrupt disable flag to `1' to disable the acceptance of other interrupts during setting.
b7 b0
1
Processor status register (PS)
Interrupt disabled
Procedure 2 Setting using interrupt enable bit to `0' (disabled)
b7 b0
00000000
Interrupt control register 1 (ICON1) [Address 00FE16]
When timer X interrupt is set, timer X interrupt is disabled. When timer Y interrupt is set, timer Y interrupt is disabled. When timer 1 interrupt is set, timer 1 interrupt is disabled. When timer 2 interrupt is set, timer 2 interrupt is disabled. When serial I/O receive interrupt is set, serial I/O receive interrupt is disabled. When serial I/O transmit interrupt is set, serial I/O transmit interrupt is disabled. When bus arbitration interrupt is set, bus arbitration interrupt is disabled. When A-D conversion completion interrupt is set, A-D conversion completion interrupt is disabled.
b7
b0
0000
Interrupt control register 2 (ICON2) [Address 00FF16]
When INT0 interrupt is set, INT0 interrupt is disabled. When INT1 interrupt is set, INT1 interrupt is disabled. When CNTR0 interrupt is set, CNTR0 interrupt is disabled. When CNTR1 interrupt is set, CNTR1 interrupt is disabled.
Procedure 3 Setting each interrupt * When INT interrupt, CNTR interrupt and key-on wakeup interrupt are used
1. Selection of edge polarity selection register
b7 b0
Edge polarity selection register (EG) [Address 00D416]
INT0 edge polarity selection INT1 edge polarity selection CNTR0 edge polarity selection CNTR1 edge polarity selection INT1 source at STP and WIT selection 0 : P31/INT1 1 : P00-P07 LOW level (Key-on wakeup) 0: Falling edge 1: Rising edge
2. When CNTR interrupt and key-on wakeup interrupt are used, using port is set to input mode. 3. When key-on wakeup interrupt is used, using port pins are pulled high. * When timer interrupt is used 1. Stop of timer count 2. Setting of each mode 3. Setting of timer (except pulse period measurement mode and pulse width measurement mode) * When serial I/O receive interrupt, serial I/O transmit interrupt or bus arbitration interrupt are used 1. Setting of registers related to serial I/O 2. Setting of baud rate generator (only when internal clock is selected as synchronous clock)
Note: For details, refer to setting of each function.
Figure 1.11.12 Setting of Interrupts (1)
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Procedure 4 Setting using interrupt request bit to `0' (no interrupt request)
b7 b0
0 00 00 000
Interrupt request register 1 (IREQ1) [Address 00FC16]
When timer X interrupt is set, there is no timer X interrupt request. When timer Y interrupt is set, there is no timer Y interrupt request. When timer 1 interrupt is set, there is no timer 1 interrupt request. When timer 2 interrupt is set, there is no timer 2 interrupt request. When serial I/O receive interrupt is set, there is no serial I/O receive interrupt request. When serial I/O transmit interrupt is set, there is no serial I/O transmit interrupt request. When bus arbitration interrupt is set, there is no bus arbitration interrupt request. When A-D conversion completion interrupt is set, there is no A-D conversion completion interrupt request.
b7
b0
0000
Interrupt request register 2 (IREQ2) [Address 00FD16]
When INT0 interrupt is set, there is no INT0 interrupt request. When INT1 interrupt is set, there is no INT1 interrupt request. When CNTR0 interrupt is set, there is no CNTR0 interrupt request. When CNTR1 interrupt is set, there is no CNTR1 interrupt request.
Procedure 5 Using interrupt enable bit to `1' (enabled)
b7 b0
1 11 11 111
Interrupt control register 1 (ICON1) [Address 00FE16]
When timer X interrupt is set, timer X interrupt is enabled. When timer Y interrupt is set, timer Y interrupt is enabled. When timer 1 interrupt is set, timer 1 interrupt is enabled. When timer 2 interrupt is set, timer 2 interrupt is enabled. When serial I/O receive interrupt is set, serial I/O receive interrupt is enabled. When serial I/O transmit interrupt is set, serial I/O transmit interrupt is enabled. When bus arbitration interrupt is set, bus arbitration interrupt is enabled. When A-D conversion completion interrupt is set, A-D conversion completion interrupt is enabled.
b7
b0
1 111
Interrupt control register 2 (ICON2) [Address 00FF16]
When INT0 interrupt is set, INT0 interrupt is enabled. When INT1 interrupt is set, INT1 interrupt is enabled. When CNTR0 interrupt is set, CNTR0 interrupt is enabled. When CNTR1 interrupt is set, CNTR1 interrupt is enabled.
Procedure 6 Setting b2 of PS to `0' when the interrupt disable flag is set to `1' in procedure 1.
b7 b0
0
Processor status register (PS)
Interrupt enabled
Procedure 7 Operate the function associated with each interrupt * When key-on wakeup interrupt is used: System is set to enter the stop mode/wait mode with the STP/WIT instruction. * When timer interrupt is used: Timer count start * When serial I/O receive interrupt, serial I/O transmit interrupt and bus arbitration interrupt are used: Data is written to the transmit buffer register and transmit/receive start. * When A-D conversion completion interrupt is used: Setting A-D control register (A-D conversion start) Note: For details, refer to setting of each function.
Figure 1.11.13 Setting of Interrupts (2)
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1.11.7 Notes on Usage Pay attention to the following notes when an interrupt is used. (1) For All Interrupts Before the execution of an interrupt, set the corresponding interrupt request bit and interrupt enable bit in the following order: Clear the interrupt request bit to `0' (no interrupt request). Set the corresponding interrupt enable bit to `1' (interrupt enabled). The interrupt request bits can be changed by software, but retain the values immediately after a rewrite instruction is executed. Therefore, the following operations must be performed after one or more instructions at the completion of a rewrite instruction: * Execute the BBC or BBS instruction after an interrupt request bit is changed. * Set an interrupt enable bit to `1' after an interrupt request bit is changed. (2) For the INT and CNTR Interrupts When edge selection bits of the edge polarity selection register are set, interrupt request bits may become `1'. Therefore, set edge selection bits in the following sequence: Clear interrupt enable bit to `0' (interrupt disabled). Set edge selection bit. Clear interrupt request bit to `0' (no interrupt request). Execute one or more instructions (NOP etc.). Set interrupt enable bit to `1' (interrupt enabled). The INT0, INT1, CNTR0, and CNTR1 pins have the alternative functions of input port pins P30, P31, I/O port pins P40, and P41, respectively. When these pins are used as input port pins, valid edges can still be detected because the 7480 Group and 7481 Group does not have the function to switch the INT and CNTR pins to input port pins. Therefore, when these pins are used as input port pins, clear all the corresponding interrupt enable bits of the INT and CNTR interrupts to `0' (disabled). Keep the trigger width input to the INT pins 250 ns or more. (3) For the Key-On Wakeup Interrupt When the key-on wakeup interrupt is used, execute the STP/WIT instruction after all inputs to port P0 are held HIGH. In states other than the stop/wait mode, the key-on wakeup interrupt is invalid. (4) For the BRK instruction interrupt When the BRK instruction is executed, 2 is added to the contents of program counter, and then the contents of the program counter are pushed onto the stack. As a result, upon return from the BRK instruction interrupt service routine, the one byte subsequent to the BRK instruction is not executed. Therefore, at programming, it is necessary to insert the NOP instruction immediately after the BRK instruction. When there are two or more interrupt sources of which interrupt request bits and interrupt enable bits are `1', but the interrupt disable flag is `1' (that is, in the interrupt disabled state), the execution of the BRK instruction starts execution of the interrupt service routine at the vector address with the highest priority level in these sources.
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1.12 Timer X and Timer Y
The 7480 Group and 7481 Group have two 16-bit timers with 16-bit latches. * Timer X * Timer Y Timer X or timer Y can select the following operation modes by the timer X or Y operation mode bits and the timer X or Y count source selection bits of the timer X mode register (address 00F616) or the timer Y mode register (address 00F716): * Timer mode * Event count mode * Pulse output mode * Pulse period measurement mode * Pulse width measurement mode * Programmable waveform generation mode * Programmable one-shot output mode * PWM mode For details, refer to the section of each mode. 1.12.1 Block Diagram Figure 1.12.1 shows the block diagram of timer X and timer Y.
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Programmable one-shot CNTR0 output mode Data bus `1' edge selection bit `0'
PWM generation circuit
`1' P30/INT0 Programmable one-shot output mode PWM mode Output level latch `001' `100' `101' `110' Timer X operating mode bits Port P40 direction register `0'
INT0 edge selection bit
Programmable one-shot output circuit
PWM mode INT0 interrupt request
Programmable waveform generation mode
DQ T
Pulse output mode
SQ T Q
`0' `1'
CNTR0 Pulse output mode edge selection bit
Port P40 latch
Timer X (low-order) latch Timer X (high-order) latch Timer X (low-order) Timer X (high-order)
Timer X interrupt request
CNTR0 edge selection bit `1' P40/CNTR0 `0'
Pulse width measurement mode Pulse period measurement mode Edge detection circuit Timer X count source selection bits CNTR0 interrupt request
f(XIN)/2 f(XIN)/8 f(XIN)/16
Programmable waveform generation mode Timer X trigger selection bit Timer X stop control bit `1' P31/INT1 Programmable one-shot output mode PWM mode Output level latch `001' `100' `101' `110' Timer Y operating mode bits Port P41 direction register Port P41 latch
DQ T D Q
`0' `1' INT1 edge selection bit
T
`0'
Programmable one-shot output circuit
PWM generation circuit
Programmable one-shot CNTR1 output mode `1' edge selection bit `0' PWM mode INT1 interrupt request
Programmable waveform generation mode Pulse output mode
SQ T Q
`0' `1'
CNTR1 Pulse output mode edge selection bit
Timer Y (low-order) latch Timer Y (high-order) latch Timer Y (low-order) Timer Y (high-order)
Timer Y interrupt request
CNTR1 edge selection bit `1' P41/CNTR1 `0'
Pulse width measurement mode Pulse period measurement mode
Edge detection circuit Timer Y count source selection bits CNTR1 interrupt request
Programmable waveform generation mode Timer Y trigger selection bit Timer Y stop control bit
f(XIN)/2 f(XIN)/8 f(XIN)/16
`0'
D T Q
`1'
Figure 1.12.1 Block Diagram of Timer X and Timer Y
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1.12.2 Registers Associated with Timer X and Timer Y Figure 1.12.2 shows the memory map of the registers associated with timer X and timer Y.
00F016 00F116 00F216 00F316
Timer X low-order (TXL) Timer X high-order (TXH) Timer Y low-order (TYL) Timer Y high-order (TYH)
00F616 00F716 00F816
Timer X mode register (TXM) Timer Y mode register (TYM) Timer XY control register (TXYCON)
Figure 1.12.2 Memory Map of Registers Associated with Timer X and Timer Y
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(1) Timer X and Timer Y These are the 16-bit registers that count the count sources. * When the timer X or Y write control bit of the timer X or Y mode register is; `0': data is written to the timer and the timer latch (Note), and `1': data is written to the timer latch only. * In the pulse width measurement mode or the pulse period measurement mode, a read from the timer receives the contents of the timer latch. In the other modes, it receives the contents of the timer. Note: The timer latches are the registers that hold the initial values automatically reloaded to the timers when they underflow, and they hold the measured values of pulse periods or widths. The timer latches cannot directly be read. Figures 1.12.3 and 1.12.4 show the timer X and timer Y.
Timer X (Timer X latch)
b7 b6 b5 b4 b3 b2 b1 b0 Timer X (high-order) (TXH) [Address 00F116] b7 b6 b5 b4 b3 b2 b1 b0 Timer X (low-order) (TXL) [Address 00F016] Function The low-order count value of timer X is indicated.
b 0 1 2 3 4 5 6 7
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note 1
b 0 1 2 3 4 5 6 7
Function The high-order count value of timer X is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note 1
Notes 1: Do not write to these bits in pulse period measurement mode or pulse width measurement mode. 2: When b3 of timer X mode register is `0', writing to latch and timer is simultaneously performed. When b3 is `1', writing to only latch is performed. 3: When reading/writing from/to timer X, read/write from/to both high-order and low-order bytes. At reading, read the high-order byte and the low-order byte in this order. At writing, write the low-order byte and the high-order byte in this order.
Figure 1.12.3 Timer X
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Timer Y (Timer Y latch)
b7 b6 b5 b4 b3 b2 b1 b0 Timer Y (high-order) (TYH) [Address 00F316] b7 b6 b5 b4 b3 b2 b1 b0 Timer Y (low-order) (TYL) [Address 00F216]
b 0 1 2 3 4 5 6 7
Function The low-order count value of timer Y is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note 1
b 0 1 2 3 4 5 6 7
Function The high-order count value of timer Y is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note 1
Notes 1: Do not write to these bits in pulse period measurement mode or pulse width measurement mode. 2: When b3 of timer Y mode register is `0', writing to latch and timer is simultaneously performed. When b3 is `1', writing to only latch is performed. 3: When reading/writing from/to timer Y, read/write from/to both high-order and low-order bytes. At reading, read the high-order byte and the low-order byte in this order. At writing, write the low-order byte and the high-order byte in this order.
Figure 1.12.4 Timer Y
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(2) Timer X Mode Register, Timer Y Mode Register, and Timer XY Control Register These registers consist of the bits controlling the operations of timer X and timer Y. Figures 1.12.5, 1.12.6, and 1.12.7 show the timer X mode register, timer Y mode register, and timer XY control register respectively.
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address 00F616]
b 0
Name Timer X operating mode bits
b2 b1 b0
Function
0 0 0 : Timer * event count mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot output mode 1 1 0 : PWM mode 1 1 1 : Not available
At reset 0
R O
W O
1
0
O
O
2
0
O
O
3 4 5
Timer X write control bit Output level latch Timer X trigger selection bit
0 : Writing to both latch and timer 1 : Writing to latch only 0 : LOW output from CNTR0 pin 1 : HIGH output from CNTR0 pin 0 : Timer X free run in programmable waveform generation mode 1 : Trigger occurrence (input signal of INT0 pin) and timer X start in programmable waveform generation mode
b7 b6
0 0 0
O O O
O O O
6 7
Timer X count source selection bits
0 0 : f(XIN)/2 0 1 : f(XIN)/8 1 0 : f(XIN)/16 1 1 : Input from CNTR0 pin
0 0
O O
O O
Figure 1.12.5 Timer X Mode Register
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1.12 Timer X and Timer Y
Timer Y mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM) [Address 00F716] b 0 Name
b2 b1 b0
Function 0 0 0 : Timer * event count mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot output mode 1 1 0 : PWM mode 1 1 1 : Not available
At reset
0
R O
W O
Timer Y operating mode bits
1
0
O
O
2
0
O
O
3 4 5
Timer Y write control bit 0 : Writing to both latch and timer 1 : Writing to latch only Output level latch Timer Y trigger selection bit 0 : LOW output from CNTR1 pin 1 : HIGH output from CNTR1 pin 0 : Timer Y free run in programmable waveform generation mode 1 : Trigger occurrence (input signal of INT1 pin) and timer Y start in programmable waveform generation mode
b7 b6
0 0 0
O O O
O O O
6 7
Timer Y count source selection bits
0 0 : f(XIN)/2 0 1 : f(XIN)/8 1 0 : f(XIN)/16 1 1 : Input from CNTR1 pin
0 0
O O
O O
Figure 1.12.6 Timer Y Mode Register
Timer XY control register
b7 b6 b5 b4 b3 b2 b1 b0
000000
Timer XY control register (TXYCON) [Address 00F816]
b 0 1 2 3 4 5 6 7
Name Timer X stop control bit Timer Y stop control bit
Function 0 : Count operation 1 : Count stop 0 : Count operation 1 : Count stop
At reset 1 1 0 0 0 0 0 0
R O O 0 0 0 0 0 0
W O O
Not implemented. Writing to these bits is disabled. These bits are `0' at reading.
x x x x x x
Figure 1.12.7 Timer XY Control Register
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1.12.3 Basic Operations of Timer X and Timer Y Basic operations of timer X and timer Y are described below. For details, refer to (1) Operations of each mode. Count Sources Timer X or timer Y can select the following count sources with the timer X or Y count source selection bits of the timer X or Y mode register: * f(XIN)/2 * f(XIN)/8 * f(XIN)/16 * CNTR0 or CNTR1 pin input (in event count mode only). Note: In the event count mode, the inverted signal of input to a CNTR pin is used as the count source when a CNTR edge selection bit of the edge polarity selection register is `1'. Writes to and Reads from Timers Write to and read from each timer two bytes together in the following order: * Write: low-order byte high-order byte * Read: high-order byte low-order byte Note: When a read from and a write into the same timer are executed during an interrupt service routine etc., the normal operation cannot be performed. Writes to timers When `TL (000016 through FFFF16)' is written to a timer, the following different operations are performed depending on the state of the timer X or Y write control bit of the timer X or Y mode register: * In the `0' state of the timer X or Y write control bit, the `TL' is set in both the timer latch and the timer. Notes 1: A write to an operating timer causes the contents of the timer to be affected, so that the time from the last underflow until the next underflow is undefined. 2: A write to the low-order byte of an operating timer allows the timer to continue counting down until the next write to the high-order byte. * In the `1' state of the timer X or Y write control bit, the `TL' is set in the timer latch only. Notes 1: A write to a stopped timer causes the contents of the timer not to be affected and allows the timer to count down from the value prior to the write. Therefore, the time from the start of count down until the first underflow is undefined. 2: If a write and an underflow occur at approximately the same time in an operating timer, the reloaded value may be undefined. Reads from timers The contents of a timer can be read by a read operation; however, the contents of the timer latch (measured value) are read in the pulse period measurement mode or the pulse width measurement mode. Note: When the high-order byte of an operating timer is read, the low-order byte is set in the latch for reading. Therefore, the read value of the low-order byte retains the value at the time the high-order byte is being read.
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Count Operation The count operation (start/stop) of timer X or timer Y is controlled by the timer X or Y stop control bit of the timer XY control register as follows: * When the timer X or Y stop control bit is set to `0', the timer starts counting. * When the timer X or Y stop control bit is set to `1', the timer stops counting. In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source. The timer X or Y stop control bit is recognized during the HIGH time of the count source. When the count has stopped, the count source cannot be accepted. In the PWM mode, the high- and the low-order bytes of timer X or Y counts down each as an 8-bit timer. Reloading Timers When a timer reaches `000016' in the count operation, an underflow occurs at the subsequent rising edge of the count source, and the contents of the timer latch are reloaded to the timer. In the pulse period measurement mode or the pulse width measurement mode, when a timer reaches `000016', an underflow occurs and a timer wraps around to `FFFF16' at the subsequent rising edge of the count source. In the PWM mode, the high- and the low-order byte of a timer count down each as an 8-bit timer. When either the high- or the low-order byte of the timer becomes `0116', an underflow occurs at the subsequent rising edge of the count source, and the contents of the timer latch are reloaded to the timer. Timer Interrupt At an underflow, the timer X or Y interrupt request bit of interrupt request register 1 is set to `1'; then a timer interrupt request is generated. Table 1.12.1 lists the relation between timer count periods and values set to timer X and timer Y. Table 1.12.1 Relation between Timer Count Periods and Values Set to Timer X and Timer Y
Clock Input Oscillation Frequency
f(XIN) = 8 MHz f(XIN)/2 (0.25 s) High- Loworder order 0F16 1F16 4E16 9C16 - - 9F16 3F16 1F16 3F16 f(XIN)/8 (1 s) High- Loworder order 0316 0716 1316 2716 C316 - E716 CF16 8716 0F16 4F16 f(XIN)/16 (2 s) High- Loworder order 0116 F316 0316 0916 1316 6116 C316 E716 C316 8716 A716 4F16 f(XIN)/2 (0.5 s) High- Loworder order 0716 0F16 2716 4E16 - - CF16 9F16 0F16 1F16
f(XIN) = 4 MHz f(XIN)/8 (2 s) High- Loworder order 0116 0316 0916 1316 6116 C316 F316 E716 C316 8716 A716 4F16 f(XIN)/16 (4 s) High- Loworder order 0016 0116 0416 0916 3016 6116 F916 F316 E116 C316 D316 A716
Count Source (Cycle Time)
Timer Period
1 2 5 10 50 100
ms ms ms ms ms ms
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1.12.4 Timer Mode and Event Count Mode (1) Operations in Timer Mode and Event Count Mode Operations in the timer mode and the event count mode are explained with Figure 1.12.8. Count Sources In the timer mode and the event count mode, timer X or timer Y can select the following count sources with the timer X or Y count source selection bits: * f(XIN)/2 timer mode * f(XIN)/8 * f(XIN)/16 * CNTR0 pin input (Timer X used) event count mode * CNTR1 pin input (Timer Y used) Notes 1: In the event count mode, the inverted signal of input to a CNTR pin is used as the count source when a CNTR edge selection bit of the edge polarity selection register is `1'. 2: In the event count mode, keep the frequency of the CNTR pin input used as the count source f(XIN)/4 or less. Writes to and Reads from Timers When `TL (000016 through FFFF16)' is written to a timer, the following different operations are performed depending on the state of the timer X or Y write control bit: * In the `0' state of the timer X or Y write control bit, the `TL' is set in both the timer latch and the timer ( in Figure 1.12.8). * In the `1' state of the timer X or Y write control bit, the `TL' is set in the timer latch only. Also, the contents of the timer can be read by a read operation. Count Operation * When the timer X or Y stop control bit of the timer XY control register is cleared to `0', the timer starts counting ( in Figure 1.12.8). * When the timer X or Y stop control bit is set to `1', the timer stops counting ( in Figure 1.12.8). In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source ( in Figure 1.12.8). Reloading Timers When a timer reaches `000016' in the count operation, an underflow occurs at the subsequent rising edge of the count source, and the contents of the timer latch are reloaded to the timer ( in Figure 1.12.8). Timer Interrupt At an underflow, the timer X or Y interrupt request bit is set to `1'; then a timer interrupt request is generated ( in Figure 1.12.8).
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Count source
(Note 2) `0' is written `1' is written `0' is written
Timer X stop control bit
Contents of timer X
Count start Writing to timer 2 X (Note 1) TL
1 5
Count start Count stop RL RL
3
4
RL
000016
6
UF
T
A
UF
UF
Time
A
Timer X interrupt request bit
A
TL : Setting value to timer X RL : Contents of timer latch is reloaded UF : Underflow T : Count period 1 T(s) = Count source frequency x (Setting value to timer X+1)
A
: Clearing by writing `0' to interrupt request bit or accepting interrupt request
Notes 1: In this case, timer X write control bit is `0' (writing to timer and timer latch simultaneously). 2: In event count mode, * when CNTR edge selection bit is `0', CNTR pin input is used as the count source. * when CNTR edge selection bit is `1', the inverted CNTR pin input is used as the count source.
Figure 1.12.8 Operation Example in Timer Mode and Event Count Mode
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(2) Setting of Timer Mode and Event Count Mode Figures 1.12.9 and 1.12.10 show the setting of the timer mode and the event count mode.
Procedure 1 Stop of timer count
b7 b0
11
Timer XY control register (TXYCON) [Address 00F816]
Timer X count stop (when timer X is used) Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin input in event counter mode
1. Setting port pin which has the alternative function of CNTR pin to input mode
b7 b0
00
(Note 1)
Port P4 direction register (P4D) [Address 00C916]
Port P40 input mode (when timer X is used) Port P41 input mode (when timer Y is used)
Notes 1: In the 7480 Group, these bits are not implemented.
b3 b2
: `Not implemented'.
2. Setting edge porality selection register
b7 b0
Edge porality selection register (EG) [Address 00D416]
CNTR0 edge porality selection (when timer X is used) CNTR1 edge porality selection (when timer Y is used) 0: CNTR pin input is used as the count source. 1: The inverted CNTR pin input is used as the count source.
Procedure 3 Setting timer mode register
* when timer X is used
b7 b0
000
Timer X mode register (TXM) [Address 00F616]
Timer * event counter mode Timer X write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Timer X count source selection 00: f(XIN)/2 01: f(XIN)/8 in timer mode 10: f(XIN)/16 11: CNTR0 pin input in event count mode
* when timer Y is used
b7 b0
000
Timer Y mode register (TYM) [Address 00F716]
Timer * event count mode Timer Y write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Timer Y count source selection 00: f(XIN)/2 in timer mode 01: f(XIN)/8 10: f(XIN)/16 in event count mode 11: CNTR1 pin input
Figure 1.12.9 Setting of Timer Mode and Event Count Mode (1)
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Procedure 4 Setting timer (Note 2)
* when timer X is used Timer X low-order (TXL) [Address 00F016] Timer X high-order (TXH) [Address 00F116] Timer X count value is set * when timer Y is used Timer Y low-order (TYL) [Address 00F216] Timer Y high-order (TYH) [Address 00F316] Timer Y count value is set
Notes 2: When writing to timer, set the low-order byte and high-order byte in this order. Procedure 5 Start of timer count
b7 b0
00
Timer XY control register (TXYCON) [Address 00F816]
Timer X count start (when timer X is used) Timer Y count start (when timer Y is used)
Figure 1.12.10 Setting of Timer Mode and Event Count Mode (2)
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1.12 Timer X and Timer Y
1.12.5 Pulse Output Mode (1) Operations in Pulse Output Mode Operations in the pulse output mode are explained with Figure 1.12.11. Count Sources In the pulse output mode, timer X or timer Y can select the following count sources with the timer X or Y count source selection bits: * f(XIN)/2 * f(XIN)/8 * f(XIN)/16 Writes to and Reads from Timers When `TL (000016 through FFFF16)' is written to a timer, the following different operations are performed depending on the state of the timer X or Y write control bit: * In the `0' state of the timer X or Y write control bit, the `TL' is set in both the timer latch and the timer ( in Figure 1.12.11). * In the `1' state of the timer X or Y write control bit, the `TL' is set in the timer latch only. Also, the contents of the timer can be read by a read operation. Count Operation * When the timer X or Y stop control bit is cleared to `0', the timer starts counting ( in Figure 1.12.11). * When the timer X or Y stop control bit is set to `1', the timer stops counting ( in Figure 1.12.11). In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source ( in Figure 1.12.11). Reloading Timers When a timer reaches `000016' in the count operation, an underflow occurs at the subsequent rising edge of the count source, and the contents of the timer latch are reloaded to the timer ( in Figure 1.12.11). Timer Interrupt At an underflow, the timer X or Y interrupt request bit is set to `1'; then a timer interrupt request is generated ( in Figure 1.12.11). Pulse Output At every underflows, polarity-inverted pulses are output from the following pins ( in Figure 1.12.11): * CNTR0 pin (Timer X used) * CNTR1 pin (Timer Y used) When the timer X or Y write control bit is `0', the CNTR pin output is initialized to the following levels by a write to the timer: * HIGH when the CNTR edge selection bit is `0' ( in Figure 1.12.11). * LOW when the CNTR edge selection bit is `1'. Notes 1: When the timer X or Y write control bit is `1', the CNTR pin output level cannot be initialized by a write to the timer. 2: In the pulse output mode, the output level of a CNTR pin is inverted when the CNTR edge selection bit is switched ( in Figure 1.12.11).
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Count source
`0' is written `1' is written `0' is written
Timer X stop control bit
Contents of timer X
Count start Writing to timer 2 X (Note 1) 4 TL
1
Count start Count stop RL
5
Writing to timer X (Note 2) RL RL
RL
3
000016
6
UF
A
UF
A
UF
A
UF Time
A
Timer X interrupt request bit
`1' is written
CNTR0 edge selection bit
Initialized when writing to timer X
8 7 9
CNTR0 pin output
Undefined H
TL : Setting value to timer X RL : Contents of timer latch is reloaded UF : Underflow H : Pulse width 1 H(s) = x (Setting value to timer X + 1) Count source frequency
A
: Clearing by writing `0' to interrupt request bit or accepting interrupt request
Notes 1: In this case, timer X write control bit is `0' (writing to timer and timer latch simultaneously). 2: In this case, timer X write control bit is `1' (writing to only timer latch).
Figure 1.12.11 Operation Example in Pulse Output Mode
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(2) Setting of Pulse Output Mode Figures 1.12.12 and 1.12.13 show the setting of the pulse output mode.
Procedure 1 Stop of timer count
b7 b0
11
Timer XY control register (TXYCON) [Address 00F816]
Timer X count stop (when timer X is used) Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin output
1. Setting port pin which has the alternative function of CNTR pin to output mode (Note 1)
b7 b0
11
(Note 2)
Port P4 direction register (P4D) [Address 00C916]
Port P40 output mode (when timer X is used) Port P41 output mode (when timer Y is used)
Notes 1: Pay attention to the output level of CNTR pin. 2: In the 7480 Group, these bits are not implemented.
b3 b2
2. Setting edge polarity selection register
b7 b0
: `Not implemented'.
Edge polarity selection register (EG) [Address 00D416]
CNTR0 edge polarity selection (when timer X is used) CNTR1 edge polarity selection (when timer Y is used) 0: When setting operation mode, HIGH level output from CNTR pin is started. 1: When setting operation mode, LOW level output from CNTR pin is started.
Procedure 3 Setting timer mode register
* when timer X is used
b7 b0
001
Timer X mode register (TXM) [Address 00F616]
Pulse output mode Timer X write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Timer X count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
* when timer Y is used
b7 b0
001
Timer Y mode register (TYM) [Address 00F716]
Pulse output mode Timer Y write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Timer Y count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
Figure 1.12.12 Setting of Pulse Output Mode (1)
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Procedure 4 Setting timer (Note 3)
* when timer X is used Timer X low-order (TXL) [Address 00F016] Timer X high-order (TXH) [Address 00F116] Timer X count value is set * when timer Y is used Timer Y low-order (TYL) [Address 00F216]
Notes 3: * When writing to timer, set the low-order byte and high-order byte in this order. * When setting count value to timer, CNTR Timer Y high-order (TYH) [Address 00F316] pin is initialized to the contents of the CNTR edge selection bit. Timer Y count value is set
Procedure 5 Start of timer count
b7 b0
00
Timer XY control register (TXYCON) [Address 00F816]
Timer X count start (when timer X is used) Timer Y count start (when timer Y is used)
Figure 1.12.13 Setting of Pulse Output Mode (2)
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1.12.6 Pulse Period Measurement Mode (1) Operations in Pulse Period Measurement Mode Operations in the pulse period measurement mode are explained with Figure 1.12.14. Count Sources In the pulse period measurement mode, timer X or timer Y can select the following count sources with the timer X or Y count source selection bits: * f(XIN)/2 * f(XIN)/8 * f(XIN)/16 Writes to and Reads from Timers In the pulse period measurement mode, do not write to timers. When a timer is read, the read value is the contents of the timer latch (measured value of the last pulse period). Count Operation * When the timer X or Y stop control bit is cleared to `0', the timer starts counting ( in Figure 1.12.14). * When the timer X or Y stop control bit is set to `1', the timer stops counting. In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source ( in Figure 1.12.14). Reloading Timers When a timer reaches `000016' in the count operation, an underflow occurs at the subsequent rising edge of the count source and a timer wraps around to `FFFF16' ( in Figure 1.12.14). When the valid edge of a CNTR pin input is detected in the count operation, the timer goes to `FFFF16' ( in Figure 1.12.14). Timer Interrupt At an underflow, the timer X or Y interrupt request bit of interrupt request register 1 is set to `1'; then a timer interrupt request is generated ( in Figure 1.12.14). CNTR Interrupt When the valid edge of a CNTR pin input is detected, the CNTR interrupt request bit of interrupt request register 2 is set to `1', and the CNTR interrupt request is generated ( in Figure 1.12.14). The measured value of the pulse period must be read at this time. Pulse Period Measurement When any one of the following valid edges are detected, the complement on one of the contents of the timer is written to the timer latch ( in Figure 1.12.14). The contents of the timer latch are retained until the measurement of the next pulse period is complete. * Valid edge of a CNTR0 pin input (Timer X used) * Valid edge of a CNTR1 pin input (Timer Y used) The measurement type of pulse period is selected by a CNTR edge selection bit of the edge polarity selection register as follows: * The period from a falling edge of a CNTR pin input until the next falling edge when the CNTR edge selection bit is `0' ( in Figure 1.12.14). * The period from a rising edge of a CNTR pin input until the next rising edge when the CNTR edge selection bit is `1'.
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* When the period from falling edge until the next falling edge is measured (Note)
CNTR0 pin input
6
T8
A A A A A
CNTR0 interrupt request bit
Count source
`0' is written
Timer X stop control bit
Count start
Contents of timer X
1 2
RL
3 4
RL
RL
RL
RL
RL
FFFF16
000016
5
UF
7 7 7 A
UF
7 A
Time
Timer X interrupt request bit RL : `FFFF16' is reloaded UF : Underflow T : Pulse period T(s) =
A
1 x {(Contents of timer latch + 1) +65536 x n} Count source frequency
n: The number of timer interrupt request generation during measuring.
: Clearing by writing `0' to interrupt request bit or accepting interrupt request
Note: In this case, CNTR0 edge selection bit is `0' (falling edge is valid).
Figure 1.12.14 Operation Example in Pulse Period Measurement Mode
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(2) Setting of Pulse Period Measurement Mode Figure 1.12.15 shows the setting of the pulse period measurement mode.
Procedure 1 Stop of timer count
b7 b0
11
Timer XY control register (TXYCON) [Address 00F816]
Timer X count stop (when timer X is used) Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin input
1. Setting port pin which has the alternative function of CNTR pin to input mode
b7 b0
00
(Note)
Port P4 direction register (P4D) [Address 00C916]
Port P40 input mode (when timer X is used) Port P41 input mode (when timer Y is used)
Note: In the 7480 Group, these bits are not implemented.
b3 b2
: `Not implemented'.
2. Setting edge polarity selection register
b7 b0
Edge polarity selection register (EG) [Address 00D416]
CNTR0 edge polarity selection (when timer X is used) CNTR1 edge polarity selection (when timer Y is used) 0: CNTR pin input from falling to falling is counted 1: CNTR pin input from rising to rising is counted
Procedure 3 Setting timer mode register
* when timer X is used
b7 b0
010
Timer X mode register (TXM) [Address 00F616]
Pulse period measurement mode Timer X count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
* when timer Y is used
b7 b0
010
Timer Y mode register (TYM) [Address 00F716]
Pulse period measurement mode Timer Y count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
Procedure 4 Start of timer count
b7 b0
00
Timer XY control register (TXYCON) [Address 00F816]
Timer X count start (when timer X is used) Timer Y count start (when timer Y is used)
Figure 1.12.15 Setting of Pulse Period Measurement Mode
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1.12.7 Pulse Width Measurement Mode (1) Operations in Pulse Width Measurement Mode Operations in the pulse width measurement mode are explained with Figure 1.12.16. Count Sources In the pulse width measurement mode, timer X or timer Y can select the following count sources with the timer X or Y count source selection bits: * f(XIN)/2 * f(XIN)/8 * f(XIN)/16 Writes to and Reads from timers In the pulse width measurement mode, do not write to timers. When a timer is read, the read value is the contents of the timer latch (measured value of the last pulse width). Count Operation * When the timer X or Y stop control bit is cleared to `0', the timer starts counting ( in Figure 1.12.16). * When the timer X or Y stop control bit is set to `1', the timer stops counting. In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source ( in Figure 1.12.16). Reloading Timers When a timer reaches `000016' in the count operation, an underflow occurs at the subsequent rising edge of the count source and a timer wraps around to `FFFF16' ( in Figure 1.12.16). When the valid edge of a CNTR pin input is detected in the count operation, the timer goes to `FFFF16' ( in Figure 1.12.16). Timer Interrupt At an underflow, the timer X or Y interrupt request bit is set to `1'; then a timer interrupt request is generated ( in Figure 1.12.16). CNTR Interrupt When the valid edge of a CNTR pin input is detected, the CNTR interrupt request bit of interrupt request register 2 is set to `1', and the CNTR interrupt request is generated ( in Figure 1.12.16). The measured value of the pulse width must be read at this time. Pulse Width Measurement When any one of the following valid edges are detected, the complement on one of the contents of the timer is written to the timer latch ( in Figure 1.12.16). The contents of the timer latch are retained until the measurement of the next pulse width is complete. * Valid edge of a CNTR0 pin input (Timer X used) * Valid edge of a CNTR1 pin input (Timer Y used) The measurement type of pulse width is selected by a CNTR edge selection bit as follows: * HIGH-level period from a rising edge of a CNTR pin input until the next falling edge when the CNTR edge selection bit is `0' ( in Figure 1.12.16). * LOW-level period from a falling edge of a CNTR pin input until the next rising edge when the CNTR edge selection bit is `1'.
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* When HIGH-level period is measured (Note)
CNTR0 pin input
6
H8
A A A
CNTR0 interrupt request bit
Count source
`0' is written
Timer X stop control bit
Count start
Contents of timer X
1 2
4
RL
3
RL
RL
RL
RL
RL
FFFF16
000016
5
UF
7
UF
7
Time
A A Timer X interrupt request bit RL : `FFFF16' is reloaded UF : Underflow H : Pulse width n: The number of timer interrupt 1 H(s) = x {(Contents of timer latch+1) + 65536 x n} request generation during measuring. Count source frequency A
: Clearing by writing `0' to interrupt request bit or accepting interrupt request
Note: In this case, CNTR0 edge selection bit is `0' (falling edge is valid).
Figure 1.12.16 Operation Example in Pulse Width Measurement Mode
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(2) Setting of Pulse Width Measurement Mode Figure 1.12.17 shows the setting of the pulse width measurement mode.
Procedure 1 Stop of timer count
b7 b0
11
Timer XY control register (TXYCON) [Address 00F816]
Timer X count stop (when timer X is used) Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin input
1. Setting port pin which has the alternative function of CNTR pin to input mode
b7 b0
00
(Note)
Port P4 direction register (P4D) [Address 00C916]
Port P40 input mode (when timer X is used) Port P41 input mode (when timer Y is used)
Note: In the 7480 Group, these bits are not implemented.
b3 b2
: `Not implemented'.
2. Setting edge polarity selection register
b7 b0
Edge polarity selection register (EG) [Address 00D416]
CNTR0 edge polarity selection (when timer X is used) CNTR1 edge polarity selection (when timer Y is used) 0: CNTR pin input from rising to falling (HIGH-level period) is counted 1: CNTR pin input from falling to rising (LOW-level period) is counted
Procedure 3 Setting timer mode register
* when timer X is used
b7 b0
011
Timer X mode register (TXM) [Address 00F616]
Pulse width measurement mode Timer X count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
* when timer Y is used
b7 b0
011
Timer Y mode register (TYM) [Address 00F716]
Pulse width measurement mode Timer Y count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
Procedure 4 Start of timer count
b7 b0
00
Timer XY control register (TXYCON) [Address 00F816]
Timer X count start (when timer X is used) Timer Y count start (when timer Y is used)
Figure 1.12.17 Setting of Pulse Width Measurement Mode
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1.12.8 Programmable Waveform Generation Mode (1) Operations in Programmable Waveform Generation Mode Operations in the programmable waveform generation mode are explained with Figure 1.12.18. Count Sources In the programmable waveform generation mode, timer X or timer Y can select the following count sources with the timer X or Y count source selection bits: * f(XIN)/2 * f(XIN)/8 * f(XIN)/16 Writes to and Reads from Timers When `TL (000016 through FFFF16)' is written to a timer, the following different operations are performed depending on the state of the timer X or Y write control bit: * In the `0' state of the timer X or Y write control bit, the `TL' is set in both the timer latch and the timer ( in Figure 1.12.18). * In the `1' state of the timer X or Y write control bit, the `TL' is set in the timer latch only ( in Figure 1.12.18). Also, the contents of the timer can be read by a read operation. Count Operation In the programmable waveform generation mode, the following starting point of a timer can be selected with the timer X or Y trigger selection bit of the timer X or Y mode register: * When a valid edge of an INT0 pin input is detected (Timer X used). * When a valid edge of an INT1 pin input is detected (Timer Y used). Clearing the timer X or Y stop control bit to `0' brings the following results: * When the timer X or Y trigger selection bit is cleared to `0', the timer starts counting. * When the timer X or Y trigger selection bit is set to `1', the timer starts counting as soon as the valid edge of an INT pin input is detected ( in Figure 1.12.18). When the timer X or Y stop control bit is set to `1', the timer stops counting. Note: Keep the trigger widths input to the INT pins 250 ns or more. In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source ( in Figure 1.12.18). Reloading Timers When a timer reaches `000016' in the count operation, an underflow occurs at the subsequent rising edge of the count source, and the contents of the timer latch are reloaded to the timer ( in Figure 1.12.18). Timer Interrupt At an underflow, the timer X or Y interrupt request bit is set to `1'; then a timer interrupt request is generated ( in Figure 1.12.18).
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1.12 Timer X and Timer Y
Generation of Programmable Waveform When an underflow occurs in a timer, the contents of the output level latches of the timer X or Y mode register are output from the following pins ( in Figure 1.12.18): * CNTR0 pin (Timer X used) * CNTR1 pin (Timer Y used) When the timer X or Y operation mode bits of the timer X or Y mode register, which are set to other modes, are switched to the programmable waveform generation mode, the CNTR pin outputs are initialized to LOW ( in Figure 1.12.18).
INT0 pin input
(Note 4)
INT0 interrupt request bit
A
A
A
Count source
`0' is written
Timer X stop control bit
Contents of timer X
Writing to timer X(Note 1) TL
1
Count start (Note 3)
3 4
Change of timer X (Note 2) RL
5
Change of timer X (Note 2)
2
RL
RL
RL
RL
000016
6
UF
UF
UF
UF
UF
Time
A
Timer X interrupt request bit
`1' is written
A
A
A
A
`0' is written
`1' is written
`0' is written
`1' is written
Output level latch
Undefined
Initialized to LOW when setting timer X operation mode bits
8 7
CNTR0 pin output
Undefined
H
TL : Setting value to timer X RL : Contents of timer latch is reloaded UF : Underflow H : Pulse width 1 H(s) = Count source frequency
A
x (Setting value to timer X+1)
: Clearing by writing `0' to interrupt request bit or accepting interrupt request
Notes 1: In this case, timer X write control bit is `0' (writing to timer and timer latch simultaneously). 2: In this case, timer X write control bit is `1' (writing to only timer latch). 3: In this case, timer X trigger selection bit is `1' (trigger occurs, at the same time, timer X is activated ). 4: In this case, INT0 edge selection bit is `1' (rising edge is valid).
Figure 1.12.18 Operation Example in Programmable Waveform Generation Mode
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1.12 Timer X and Timer Y
(2) Setting of Programmable Waveform Generation Mode Figures 1.12.19 and 1.12.20 show the setting of the programmable waveform generation mode.
Procedure 1 Stop of timer count
b7 b0
11
Timer XY control register (TXYCON) [Address 00F816]
Timer X count stop (when timer X is used) Timer Y count stop (when timer Y is used)
Procedure 2 Setting INT pin input and CNTR pin output
1. Setting port pin which has the alternative function of the CNTR pin to output mode (Note 1)
b7 b0
11
(Note 2)
Port P4 direction register (P4D) [Address 00C916]
Port P40 output mode (when timer X is used) Port P41 output mode (when timer Y is used)
Notes 1: Pay attention to the output level of CNTR pin. 2: In the 7480 Group, these bits are not implemented.
b3 b2
: `Not implemented'.
2. Setting INT edge selection bit when timer is activated by the trigger of INT pin input
b7 b0
Edge polarity selection register (EG) [Address 00D416]
INT0 edge polarity selection (when timer X is used) INT1 edge polarity selection (when timer Y is used) 0: Timer is activated by detecting the falling edge of INT pin input 1: Timer is activated by detecting the rising edge of INT pin input
Procedure 3 Setting timer mode register
* when timer X is used
b7 b0
100
Timer X mode register (TXM) [Address 00F616]
Programmable waveform generation mode (Note 3) Timer X write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Output level latch Timer X trigger selection 0: Timer X free run 1: Trigger occurrence (input signal of INT0 pin) and timer X start Timer X count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
Notes 3: The CNTR pin output is initialized to LOW when the operation mode bits set to other modes are set to the programmable waveform generation mode.
Figure 1.12.19 Setting of Programmable Waveform Generation Mode (1)
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* when timer Y is used
b7 b0
100
Timer Y mode register (TYM) [Address 00F716]
Programmable waveform generation mode (Note 3) Timer Y write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Output level latch Timer Y trigger selection 0: Timer Y free run 1: Trigger occurrence (input signal of INT1 pin) and timer Y start Timer Y count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
Procedure 4 Setting timer (Note 4)
* when timer X is used Timer X low-order (TXL) [Address 00F016] Timer X high-order (TXH) [Address 00F116] Timer X count value is set * when timer Y is used Timer Y low-order (TYL) [Address 00F216] Timer Y high-order (TYH) [Address 00F316] Timer Y count value is set
Notes 4: When writing to timer, set the low-order byte and high-order byte in this order. Procedure 5 Start of timer count (Note 5)
b7 b0
00
Timer XY control register (TXYCON) [Address 00F816]
Timer X count start (when timer X is used) Timer Y count start (when timer Y is used)
Notes 5: When bit 5 of timer mode register is `1', timer count does not start at this time. Trigger (input signal of INT pin) occurs, at the same time, timer count starts. Notes 6: Keep the trigger width input to INT pin 250 ns or more.
Figure 1.12.20 Setting of Programmable Waveform Generation Mode (2)
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1.12 Timer X and Timer Y
1.12.9 Programmable One-Shot Output Mode (1) Operations in Programmable One-Shot Output Mode Operations in the programmable one-shot output mode is explained with Figure 1.12.21. Count Sources In the programmable one-shot output mode, timer X or timer Y can select the following count sources with the timer X or Y count source selection bits: * f(XIN)/2 * f(XIN)/8 * f(XIN)/16 Writes to and Reads from Timers When `TL (000016 through FFFF16)' is written to a timer, the following different operations are performed depending on the state of the timer X or Y write control bit: * In the `0' state of the timer X or Y write control bit, the `TL' is set in both the timer latch and the timer ( in Figure 1.12.21). * In the `1' state of the timer X or Y write control bit, the `TL' is set in the timer latch only. Also, the contents of the timer can be read by a read operation. Count Operation * When the timer X or Y stop control bit is cleared to `0', the timer starts counting ( in Figure 1.12.21). * When the timer X or Y stop control bit is set to `1', the timer stops counting. In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source ( in Figure 1.12.21). Reloading Timers When a timer reaches `000016' in the count operation, an underflow occurs at the subsequent rising edge of the count source, and the contents of the timer latch are reloaded to the timer ( in Figure 1.12.21). When the valid edge of an INT pin input is detected, the contents of the timer latch are also reloaded ( in Figure 1.12.21). Timer Interrupt At an underflow, the timer X or Y interrupt request bit is set to `1'; then a timer interrupt request is generated ( in Figure 1.12.21). Generation of Programmable One-Shot Pulse * When timer X is used, a one-shot pulse is output from the CNTR0 pin when the valid edge of an INT0 pin input is detected ( in Figure 1.12.21). * When timer Y is used, a one-shot pulse is output from the CNTR1 pin when the valid edge of an INT1 pin input is detected.
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When the timer X or Y operation mode bits of the timer X or Y mode register are set to the programmable one-shot output mode, the CNTR pin outputs are initialized to the content of the CNTR edge selection bit ( in Figure 1.12.21). The CNTR pin output remains at the inverted level of the content of the CNTR edge selection bit for the period from the rising edge1 of the count source immediately after the valid edge of an INT pin input is detected until the subsequent an underflow ( in Figure 1.12.21). Notes 1: Keep the trigger widths input to the INT pins 250 ns or more. 2: In the programmable one-shot output mode, the output level of a CNTR pin is inverted when the CNTR edge selection bit is switched ( in Figure 1.12.21). 1: One cycle or less of the rising edge of the count source, after the valid edge of an INT pin input is detected.
INT0 pin input
(Note 2)
INT0 interrupt request bit
A
A
A
Count source
`0' is written
Timer X stop control bit
Count start Writing to timer X 2 (Note 1) 3 RL TL
1 5 4
Contents of timer X
RL
RL
RL
RL
RL
000016
6
UF
A
UF
A
UF
A
Time
Timer X interrupt request bit
`0' is written
CNTR0 edge selection bit
Initialized to the contents of CNTR0 edge selection bit when setting timer X operation mode bits
8 7 10
CNTR0 pin output
Undefined H9
TL : Setting value to timer X RL : Contents of timer latch is reloaded UF : Underflow H : Pulse width 1 H(s) = Count source frequency x (Setting value to timer X + 1)
A
: Clearing by writing `0' to interrupt request bit or accepting interrupt request
Notes 1: In this case, timer X write control bit is `0' (writing to timer and timer latch simultaneously). 2: In this case, INT0 edge selection bit is `1' (rising edge is valid).
Figure 1.12.21 Operation Example in Programmable One-Shot Output Mode
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1.12 Timer X and Timer Y
(2) Setting of Programmable One-Shot Output Mode Figures 1.12.22 and 1.12.23 show the setting of the programmable one-shot output mode.
Procedure 1 Stop of timer count
b7 b0
11
Timer XY control register (TXYCON) [Address 00F816]
Timer X count stop (when timer X is used) Timer Y count stop (when timer Y is used)
Procedure 2 Setting INT pin input and CNTR pin output
1. Setting port pin which has the alternative function of the CNTR pin to output mode (Note 1)
b7 b0
11
(Note 2)
Port P4 direction register (P4D) [Address 00C916]
Port P40 output mode (when timer X is used) Port P41 output mode (when timer Y is used)
Notes 1: Pay attention to the output level of CNTR pin. 2: In the 7480 Group, these bits are not implemented.
b3 b2
: `Not implemented'.
2. Setting INT edge selection bit and CNTR edge selection bit
b7 b0
Edge polarity selection register (EG) [Address 00D416]
INT0 edge polarity selection (when timer X is used) INT1 edge polarity selection (when timer Y is used) 0: Falling edge of INT pin input detected 1: Rising edge of INT pin input detected CNTR0 edge polarity selection (when timer X is used) CNTR1 edge polarity selection (when timer Y is used) 0: HIGH level from CNTR pin is output after the maximum 1 cycle of count source from trigger detection of INT pin input. 1: LOW level from CNTR pin is output after the maximum 1 cycle of count source from trigger detection of INT pin input.
Procedure 3 Setting timer mode register
* when timer X is used
b7 b0
101
Timer X mode register (TXM) [Address 00F616]
Programmable one-shot output mode (Note 3) Timer X write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Timer X count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
Notes 3: When setting operation mode, CNTR pin output is initialized to the contents of the CNTR edge selection bit.
Figure 1.12.22 Setting of Programmable One-Shot Output Mode (1)
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* when timer Y is used
b7 b0
101
Timer Y mode register (TYM) [Address 00F716]
Programmable one-shot output mode (Note 3) Timer Y write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Timer Y count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
Procedure 4 Setting timer (Note 4)
* when timer X is used Timer X low-order (TXL) [Address 00F016] Timer X high-order (TXH) [Address 00F116] Timer X count value is set * when timer Y is used Timer Y low-order (TYL) [Address 00F216] Timer Y high-order (TYH) [Address 00F316] Timer Y count value is set
Notes 4: When writing to timer, set the low-order byte and high-order byte in this order. Procedure 5 Start of timer count
b7 b0
00
Timer XY control register (TXYCON) [Address 00F816]
Timer X count start (when timer X is used) Timer Y count start (when timer Y is used)
Notes 5: Keep the trigger width input to INT pin 250 ns or more.
Figure 1.12.23 Setting of Programmable One-Shot Output Mode (2)
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1.12.10 PWM Mode (1) Operations in PWM Mode Operations in the PWM mode are explained with Figure 1.12.24. Count Sources In the PWM mode, timer X or timer Y can select the following count sources with the timer X or Y count source selection bits: * f(XIN)/2 * f(XIN)/8 * f(XIN)/16 Writes to and Reads from Timers When `TL (000016 through FFFF16)' is written to a timer, the following different operations are performed depending on the state of the timer X or Y write control bit: * In the `0' state of the timer X or Y write control bit, the `TL' is set in both the timer latch and the timer ( in Figure 1.12.24). * In the `1' state of the timer X or Y write control bit, the `TL' is set in the timer latch only. Also, the contents of the timer can be read by a read operation. Count Operation In the PWM mode, the high- and the low-order byte of a timer counts down each as an 8-bit timer. * When the timer X or Y stop control bit is cleared to `0' in the HIGH state of the PWM output, only the high-order byte of the timer starts counting down ( in Figure1.12.24), while in the LOW state of the PWM output, only the low-order byte of the timer starts counting down ( in Figure 1.12.24). * When the stop control bit is set to `1', both the high- and the low-order byte stop counting down ( in Figure 1.12.24). In the count operation, the contents of the high- or the low-order byte of the timer are decremented by 1 at every rising edge of the count source ( in Figure 1.12.24). When either the high- or the low-order byte of an operating timer becomes `0116', it stops counting. At the same time, the other starts counting ( in Figure 1.12.24). Reloading Timers When either the high- or the low-order byte of an operating timer becomes `0116', an underflow occurs at the subsequent rising edge of the count source, and the contents of the timer latch is reloaded to the timer ( in Figure 1.12.24). Timer Interrupt At an rising edge of the PWM output waveform, the timer X or Y interrupt request bit is set to `1'; then a timer interrupt request is generated ( in Figure 1.12.24). PWM Output * When timer X is used, the PWM waveform is output from the CNTR0 pin. * When timer Y is used, the PWM waveform is output from the CNTR1 pin.
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When the timer X or Y write control bit is `0', the CNTR pin output is initialized to HIGH by a write to the timer ( in Figure 1.12.24). When it is `1', however, the CNTR pin output level cannot be initialized by a write to the timer. In the PWM mode, when the low-order byte of the timer becomes `0116' in the LOW level of the PWM output ( in Figure 1.12.24), or when the high-order byte becomes `0116' in the HIGH level of the PWM output ( in Figure 1.12.24), an underflow occurs in each timer at the subsequent rising edge of the count source and the output level of the CNTR pin is inverted. When `TLL (0016 through FF16)' is written to the low-order byte of the timer and `TLH (0016 through FF16)' to the high-order byte, the duty cycle of the PWM waveform output from the CNTR pin is expressed by `TLH/(TLH + TLL)'. Notes 1: * All of the PWM outputs are HIGH when TLL = 0016 and TLH 0016. * All of the PWM outputs are LOW when TLH = 0016. 2: When at least one of TLL and TLH is `0016', no timer interrupt request can be generated. 3: Even when value `0016' is written to a timer, the timer continues counting down. Therefore, the contents of the timer are undefined.
Count source
`0' is written `1' is written `0' is written
Timer X stop control bit
Contents of timer X Contents of timer X (hjgh-order) (low-order)
Count start Writing to timer X (high-order) (Note) TLH
1 2 5
Count start Count stop RL RL RL 4
3
RL
0116 0016 Writing to timer X (low-order) (Note) TLL 0116 0016
1
UF
6
UF
UF
UF Time
RL
RL
RL
UF
7 A
UF
A
UF
A
Time
Timer X interrupt request bit
Initialized to HIGH when writing to timer X (Note)
8
9
HH T
10
HL
CNTR0 pin output
Undefined
TLH TLL T HH
: Setting value to timer X (high-order) : Setting value to timer X (low-order) RL : Contents of timer latch is reloaded UF : Underflow : PWM period T(s)=HH + HL : Pulse width (HIGH-period) 1 x Setting value to timer X (high-order) HH(s) = Count source frequency HL : Pulse width (LOW-period) 1 HL(s) = x Setting value to timer X (low-order) Count source frequency
A
: Clearing by writing `0' to interrupt request bit or accepting interrupt request
Note: In this case, timer X write control bit is `0' (writing to timer and timer latch simultaneously).
Figure 1.12.24 Operation Example in PWM Mode
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(2) Setting of PWM Mode Figures 1.12.25 and 1.12.26 show the setting of the PWM mode.
Procedure 1 Stop of timer count
b7 b0
11
Timer XY control register (TXYCON) [Address 00F816]
Timer X count stop (when timer X is used) Timer Y count stop (when timer Y is used)
Procedure 2 Setting CNTR pin output (Setting the port pin which has the alternative function of CNTR pin to output mode) (Note 1)
b7 b0
11
(Note 2)
Port P4 direction register (P4D) [Address 00C916]
Port P40 output mode (when timer X is used) Port P41 output mode (when timer Y is used)
Notes 1: Pay attention to the output level of CNTR pin. 2: In the 7480 Group, these bits are not implemented.
b3 b2
: `Not implemented'. Procedure 3 Setting timer mode register
* when timer X is used
b7 b0
110
Timer X mode register (TXM) [Address 00F616]
PWM mode (Note 3) Timer X write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Timer X count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
* when timer Y is used
b7 b0
110
Timer Y mode register (TYM) [Address 00F716]
PWM mode (Note 3) Timer Y write control 0: Writing to latch and timer simultaneously 1: Writing to only latch Timer Y count source selection 00: f(XIN)/2 01: f(XIN)/8 10: f(XIN)/16 11: Not available
Notes 3: When setting operation mode, CNTR pin output is initialized to HIGH.
Figure 1.12.25 Setting of PWM Mode (1)
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Procedure 4 Setting timer (Note 4)
* when timer X is used Timer X low-order (TXL) [Address 00F016] Timer X low-order count value (LOW level output interval) is set Timer X high-order (TXH) [Address 00F116] Timer X high-order count value (HIGH level output interval) is set * when timer Y is used Timer Y low-order (TYL) [Address 00F216] Timer Y low-order count value (LOW level output interval) is set Timer Y high-order (TYH) [Address 00F316] Timer Y high-order count value (HIGH level output interval) is set
Notes 4: When writing to timer, set the low-order byte and high-order byte in this order. Procedure 5 Start of timer count
b7 b0
00
Timer XY control register (TXYCON) [Address 00F816]
Timer X count start (when timer X is used) Timer Y count start (when timer Y is used)
Figure 1.12.26 Setting of PWM Mode (2)
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1.12.11 Notes on Usage Pay attention to the following notes when timer X or Y is used. (1) In All Modes Write to and Read from Timers Write to and read from each timer two bytes together in the following order: * Write: low-order byte high-order byte * Read: high-order byte low-order byte When a read from and a write into the same timer are executed during an interrupt service routine etc., the normal operation cannot be performed. In the pulse period measurement mode and the pulse width measurement mode, do not write to timers. Writes to Timers When the timer X or Y write control bit is `0': * A write to an operating timer causes the contents of the timer to be affected, so that the time from the last underflow until the next underflow is undefined in this case. * A write to the low-order byte of an operating timer allows the timer to continue counting down until the next write to the high-order byte. Therefore, the time until the subsequent underflow may be undefined. Figure 1.12.27 shows an operation in timer X or timer Y at writes.
* Example: Writing `020016' into timer
Count source
Contents of timer (low-order)
Undefined value
0016
FF16
FE16
FD16
Contents of timer (high-order)
Undefined value
`0016' is written to the low-order of timer `0216' is written to the high-order of timer
0216
Note: In this case, the write control bit is `0'.
Figure 1.12.27 Operation in Timer X or Timer Y at Writes When the timer X or Y write control bit is `1': * A write to a stopped timer causes the contents of the timer not to be affected and allows the timer to count down from the value prior to this write. Therefore, the time from the start of count down until the first underflow is undefined. * If a write and an underflow occur at approximately the same time in an operating timer, the reloaded value may be undefined.
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Reads from Timers * When the high-order byte of an operating timer is read, the low-order byte is set in the latch for reading. Therefore, the read value of the low-order byte retains the value at the time the high-order byte is being read. * In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source, while the contents of each timer are transferred to the latch for reading by falling edge, so that the read value of the timer may be different from its real value. Figure 1.12.28 shows an operation in timer X or timer Y at reads.
Count source Contents of timer
010116 010216
010016 010116
00FF16 010016
00FE16
00FD16
Read value of timer
00FF16
00FE16
High-order of timer is read (Read value: `0116') In this case, the low-order read value `0116' is written to latch for reading.
Low-order of timer is read (Read value: `0116')
Figure 1.12.28 Operation in Timer X or Timer Y at Reads (2) In Event Count Mode The inverted signal of input to a CNTR pin is used as the count source when a CNTR edge selection bit of the edge polarity selection register is `1'. Keep the frequency of the CNTR pin input used as the count source f(XIN)/4 or less. (3) In Pulse Output Mode When the timer X or Y write control bit is `0', the CNTR pin output is initialized to the following levels by a write to the timer: * HIGH when the CNTR edge selection bit is `0'. * LOW when the CNTR edge selection bit is `1'. When the timer X or Y write control bit, however, is `1', the CNTR pin output level cannot be initialized by a write to the timer. The output level of a CNTR pin is inverted when the CNTR edge polarity selection bit is switched. (4) In Pulse Period Measurement Mode and Pulse Width Measurement Mode Do not write to timers in these modes; otherwise the last measured value in the timer latch will be changed by this write. When a timer is read, the read value is the contents of the timer latch (the last measured value). (5) In Programmable Waveform Generation Mode When the timer X or Y operation mode bits, which are set to other modes, are switched to the programmable waveform generation mode, the CNTR pin outputs are initialized to LOW. When the timer X or Y trigger selection bit is `1', keep the trigger widths input to the INT pins 250ns or more.
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1.12 Timer X and Timer Y
(6) In Programmable One-Shot Output Mode When the timer X or Y operation mode bits are set to the programmable one-shot output mode, the CNTR pin outputs are initialized to the content of the CNTR edge selection bit. The output level of a CNTR pin is inverted when the CNTR edge selection bit is switched. Keep the trigger widths input to the INT pins 250 ns or more. (7) In PWM Mode When the timer X or Y write control bit is `0', the CNTR pin output is initialized to HIGH by a write to the timer. When the write control bit is `1', the CNTR pin output level cannot be initialized by a write to the timer. All of the PWM outputs are HIGH when TLL = 0016 and TLH 0016. All of the PWM outputs are LOW when TLH = 0016. When at least one of TLL and TLH is `0016', no timer interrupt request can be generated. Even when value `0016' is written to a timer, the timer continues counting down. Therefore, the contents of the timer are undefined. (8) I/O Port Pins P40 and P41 with the Alternative Functions of Timer I/O Pins CNTR0 and CNTR1 Port pins P40 and P41 have the alternative functions of 16-bit timer I/O pins CNTR0 and CNTR1 respectively. If the timer X or Y operation mode bit of the corresponding timer is set to any mode related to output (Note), these pins cannot perform the normal function as output port pins. Refer to Figure 1.10.3 Block Diagrams of Port Pins P2i to P5i in Section 1.10. Input/Output Pins. Note: Modes related to output: * Pulse output mode * Programmable waveform generation mode * Programmable one-shot output mode * PWM mode (9) Edge Polarity Selection Register When the edge polarity selection bit of edge polarity selection register is set, the interrupt request bit may be set to `1'. Refer to Section 1.11.7 (2) in 1.11 Interrupts.
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1.13 Timer 1 and Timer 2
1.13 Timer 1 and Timer 2
The 7480 Group and 7481 Group have two 8-bit timers with 8-bit latches: * Timer 1 * Timer 2 Timer 1 or timer 2 can select the following operation modes by the timer 1 or 2 operation mode bit of the timer 1 mode register (address 00F916) or the timer 2 mode register (address 00FA16): * Timer mode * Programmable waveform generation mode For details, refer to the section of each mode. 1.13.1 Block Diagram Figure 1.13.1 shows the block diagram of timer 1 and timer 2.
Data bus
8
f(XIN)/8 f(XIN)/64 f(XIN)/128 f(XIN)/256
Timer count source selection bits `00' Timer stop `01' control bit `10' `11'
T
TL
8
Timer interrupt request bit
T
T0, T1 output
Q
D
Output level latch
8
Timer mode register
8
Data bus
Figure 1.13.1 Block Diagram of Timer 1 and Timer 2 1.13.2 Registers Associated with Timer 1 and Timer 2 Figure 1.13.2 shows the memory map of the registers associated with timer 1 and timer 2.
00F416 00F516
Timer 1 (T1) Timer 2 (T2)
00F916 Timer 1 mode register (T1M) 00FA16 Timer 2 mode register (T2M)
Figure 1.13.2 Memory Map of Registers Associated with Timer 1 and Timer 2
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(1) Timer 1 and Timer 2 These are the 8-bit registers that count the pulses of count sources. * When a timer is written, the written data is set to the timer and the timer latch (Note). * When a timer is read, the read value is the contents of the timer. Note: The timer latches are the registers that hold the initial values automatically reloaded to the timers when they underflow. Actually, the value decremented by 1 from the contents of the timer latch is reloaded to the timer. Figures 1.13.3 and 1.13.4 show the timer 1 and timer 2.
Timer 1 (Timer 1 latch)
b7 b6 b5 b4 b3 b2 b1 b0 Timer1 (T1) [Address 00F416]
b 0 1 2 3 4 5 6 7
Function The timer 1 count value is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W O O O O O O O O
Figure 1.13.3 Timer 1
Timer 2 (Timer 2 latch)
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address 00F516]
b 0 1 2 3 4 5 6 7
Function The timer 2 count value is indicated.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R O O O O O O O O
W O O O O O O O O
Figure 1.13.4 Timer 2
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(2) Timer 1 Mode Register and Timer 2 Mode Register These registers consist of the bits controlling the operation of timer 1 and timer 2. Figures 1.13.5 and 1.13.6 show the timer 1 and 2 mode registers.
Timer 1 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Timer 1 mode register (T1M) [Address 00F916]
b 0 1 2 3 4 5 6 7
Name Timer 1 stop control bit Timer 1 operation mode bit
Function 0 : Count operation 1 : Count stop 0 : Timer mode 1 : Programmable waveform generation mode
At reset 0 0 0 0 0 0 0 0
R O O 0 0 O 0 O O
W O O
Not implemented. Writing to these bits is disabled. These bits are `0' at reading. Output level latch 0 : LOW output from T0 pin 1 : HIGH output from T0 pin
x x
O
Not implemented. Writing to this bit is disabled. This bit is `0' at reading. Timer 1 count source selection bits
b7 b6
x
O O
0 0 : f(XIN)/8 0 1 : f(XIN)/64 1 0 : f(XIN)/128 1 1 : f(XIN)/256
Figure 1.13.5 Timer 1 Mode Register
Timer 2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Timer 2 mode register (T2M) [Address 00FA16]
b 0 1 2 3 4 5 6 7
Name Timer 2 stop control bit Timer 2 operation mode bit
Function 0 : Count operation 1 : Count stop 0 : Timer mode 1 : Programmable waveform generation mode
At reset 0 0 0 0 0 0 0 0
R O O 0 0 O 0 O O
W O O
Not implemented. Writing to these bits is disabled. These bits are `0' at reading. Output level latch 0 : LOW output from T1 pin 1 : HIGH output from T1 pin
x x
O
Not implemented. Writing to this bit is disabled. This bit is `0' at reading. Timer 2 count source selection bits
b7 b6
x
O O
0 0 : f(XIN)/8 0 1 : f(XIN)/64 1 0 : f(XIN)/128 1 1 : f(XIN)/256
Figure 1.13.6 Timer 2 Mode Register
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1.13 Timer 1 and Timer 2
1.13.3 Basic Operations of Timer 1 and Timer 2 Basic operations of timer 1 and timer 2 are described below. For details, refer to (1) Operations of each mode. Count Sources Timer 1 and timer 2 can select the following count sources with the timer 1 or 2 count source select bits of the timer 1 or 2 mode register: * f(XIN)/8 * f(XIN)/64 * f(XIN)/128 * f(XIN)/256 Writes to Timers When `TL(0016 through FF16)' is written to a timer, `TL' is set in both the timer and the timer latch. Note: A write to an operating timer causes the contents of the timer to be affected, so that the period from the last underflow until the next underflow is undefined. Reads from Timers The contents of the timer can be read by a read operation. Count Operations The count operation (start/stop) of timer 1 or timer 2 is controlled by the timer 1 or 2 stop control bit of the timer 1 or 2 mode register as follows: * When the timer 1 or 2 stop control bit is set to `0', the timer starts counting. * When the timer 1 or 2 stop control bit is set to `1', the timer stops counting. In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source. The timer 1 or 2 stop control bit is recognized during the HIGH time of the count source. When the count has stopped, the count source cannot be accepted. Reloading Timers When a timer reaches `FF16' in the count operation, an underflow occurs at the subsequent rising edge of the count source, and the value decremented by 1 from the contents of the timer latch is reloaded to the timer. Timer Interrupt At an underflow, the timer 1 or 2 interrupt request bit of interrupt request register 1 is set to `1'; then a timer interrupt request is generated. Table 1.13.1 lists the relation between timer count periods and values set to timer 1 and timer 2.
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Table 1.13.1 Relation between Timer Count Periods and Values Set to Timer 1 and Timer 2
Clock Input Oscillation Frequency
f(XIN) = 8 MHz f(XIN)/8 (1s) 6316 C716 -- -- -- -- f(XIN)/64 (8s) -- 1816 -- 7C16 F916 -- f(XIN)/128 (16s) -- -- -- -- 7C16 F916 f(XIN)/256 (32s) -- -- -- -- -- 7C16 f(XIN)/8 (2s) 3116 6316 F916 -- -- --
f(XIN) = 4 MHz f(XIN)/64 (16s) -- -- -- -- 7C16 F916 f(XIN)/128 (32s) -- -- -- -- -- 7C16
Count Source (Count Period) Timer Period 100 s 200 s 500 s 1 ms 2 ms 4 ms
1.13.4 Timer Mode (1) Operations in Timer Mode The operations in the timer mode is explained with Figure 1.13.7. Count Sources In the timer mode, timer 1 or timer 2 can select the following count sources with the timer 1 or 2 count source selection bits of the timer 1 or 2 mode register: * f(XIN)/8 * f(XIN)/64 * f(XIN)/128 * f(XIN)/256
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Writes to and Reads from Timer When `TL (0016 through FF16)' is written to a timer, `TL' is set in both the timer and the timer latch ( in Figure 1.13.7). Also, the contents of the timer can be read by a read operation. Count Operation * When the timer 1 or 2 stop control bit is cleared to `0', the timer starts counting ( in Figure 1.13.7). * When the timer 1 or 2 stop control bit is set to `1', the timer stops counting ( in Figure 1.13.7). In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source ( in Figure 1.13.7). Reloading Timers When a timer reaches `FF16' in the count operation, an underflow occurs at the subsequent rising edge of the count source, and the value decremented by 1 from the contents of the timer latch is reloaded to the timer. ( in Figure 1.13.7). Timer Interrupt At an underflow, the timer 1 or 2 interrupt request bit is set to `1'; then a timer interrupt request is generated ( in Figure 1.13.7).
Count source
`0' is written `1' is written `0' is written
Timer 1 stop control bit
Count start
Contents of timer 1
Writing to timer 1 TL TL-1
1
2 4
Count start Count stop Writing to timer 1
3
RL
5
RL
RL
RL
0016 FF16
6
UF
T
A
UF
UF
UF Time
A A
Timer 1 interrupt request bit
A
TL : Setting value to timer 1 RL : The value which is the timer latch decremented by 1 is reloaded UF : Underflow 1 x (Setting value to timer 1 +1) T : Count period T(s) = Count source frequency
A
: Clearing by writing `0' to interrupt request bit or accepting interrupt request
Figure 1.13.7 Operations in Timer Mode
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(2) Setting of Timer Mode Figure 1.13.8 shows the setting of the timer mode.
Procedure 1 Stop of timer count
* when timer 1 is used
b7 b0
1
Timer 1 mode register (T1M) [Address 00F916] Timer 1 count is stopped.
* when timer 2 is used
b7 b0
1
Timer 2 mode register (T2M) [Address 00FA16] Timer 2 count is stopped.
Procedure 2 Setting timer mode register
* when timer 1 is used
b7 b0
01
Timer 1 mode register (T1M) [Address 00F916]
Timer mode Timer 1 count source selection 00: f(XIN)/8 01: f(XIN)/64 10: f(XIN)/128 11: f(XIN)/256
* when timer 2 is used
b7 b0
01
Timer 2 mode register (T2M) [Address 00FA16]
Timer mode Timer 2 count source selection 00: f(XIN)/8 01: f(XIN)/64 10: f(XIN)/128 11: f(XIN)/256
Note : Procedure 1 and 2 can be set simultaneously because the described register is the same. Procedure 3 Setting timer
* when timer 1 is used Timer 1 (T1) [Address 00F416]
Timer 1 count value is set
* when timer 2 is used Timer 2 (T2) [Address 00F516]
Timer 2 count value is set
Procedure 4 Start of timer count
* when timer 1 is used
b7 b0
00 * when timer 2 is used
b7 b0
Timer 1 mode register (T1M) [Address 00F916]
Timer 1 count is started
00
Timer 2 mode register (T2M) [Address 00FA16]
Timer 2 count is started
Figure 1.13.8 Setting of Timer Mode
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1.13 Timer 1 and Timer 2
1.13.5 Programmable Waveform Generation Mode (1) Operations in Programmable Waveform Generation Mode Operations in the programmable waveform generation mode is explained with Figure 1.13.9. Count Sources In the programmable waveform generation mode, timer 1 or timer 2 can select the following count sources with the timer 1 or 2 count source selection bits: * f(XIN)/8 * f(XIN)/64 * f(XIN)/128 * f(XIN)/256 Writes to and Reads from Timers When `TL(0016 through FF16)' is written to a timer, `TL' is set in both the timer and the timer latch ( in Figure 1.13.9). Also, the contents of the timer can be read by a read operation. Count Operation * When the timer 1 or 2 stop control bit is cleared to `0', the timer starts counting ( in Figure 1.13.9). * When the timer 1 or 2 stop control bit is set to `1', the timer stops counting ( in Figure 1.13.9). In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source ( in Figure 1.13.9). Reloading timers When a timer reaches `FF16' in the count operation, an underflow occurs at the subsequent rising edge of the count source, and the value decremented by 1 from the contents of the timer latch is reloaded to the timer. ( in Figure 1.13.9). Timer interrupt At an underflow, the timer 1 or 2 interrupt request bit is set to `1'; then a timer interrupt request is generated ( in Figure 1.13.9). Generation of Programmable Waveform When an underflow occurs in a timer, the contents of the output level latch are output from the following pins ( in Figure 1.13.9): * T0 pin (Timer 1 used) * T1 pin (Timer 2 used) The output level of the T0 or T1 pin remains undefined until the first underflow occurs in this mode ( in Figure 1.13.9).
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Count source
`0' is written `1' is written `0' is written
Timer 1 stop control bit
Count start Writing TL to timer 1
2
Count start Writing TL to timer 1 Writing TL to timer 1 RL
4
Contents of timer 1
TL' TL' - 1
Count stop
3
TL TL - 1 0016 FF16
1 5
RL
RL
RL
UF
6 A
UF
A
UF
A
UF
Time
A
Timer 1 interrupt request bit
`1' is written
`0' is written
`1' is written
`0' is written
`1' is written
Output level latch
Undefined
8
7
T0 pin output
Undefined H
A
: Clearing by writing `0' to interrupt request bit or accepting interrupt request
TL : Setting value to timer 1 RL : The value which is the timer latch decremented by 1 is reloaded UF : Underflow 1 H : Pulse width H(s) = Count source frequency x (Setting value to timer 1 +1)
Figure 1.13.9 Operations in Programmable Waveform Generation Mode
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(2) Setting of Programmable Waveform Generation Mode Figures 1.13.10 and 1.13.11 show the setting of the programmable waveform generation mode.
Procedure 1 Stop of timer count
* when timer 1 is used
b7 b0
1
Timer 1 mode register (T1M) [Address 00F916] Timer 1 count is stopped.
* when timer 2 is used
b7 b0
1
Timer 2 mode register (T2M) [Address 00FA16] Timer 2 count is stopped.
Procedure 2 Setting port which is also used as T pin to output mode (Note 1)
b7 b0
00
Port P1 direction register (P1D) [Address 00C316] Port P12 output mode (when timer 1 is used) Port P13 output mode (when timer 2 is used)
Notes 1: Pay attention to the output level of T pin. Procedure 3 Setting timer mode register
* when timer 1 is used
b7 b0
11
Timer 1 mode register (T1M) [Address 00F916]
Programmable waveform generation mode Output level latch Timer 1 count source selection 00: f(XIN)/8 01: f(XIN)/64 10: f(XIN)/128 11: f(XIN)/256
* when timer 2 is used
b7 b0
11
Timer 2 mode register (T2M) [Address 00FA16]
Programmable waveform generation mode Output level latch Timer 2 count source selection 00: f(XIN)/8 01: f(XIN)/64 10: f(XIN)/128 11: f(XIN)/256
Notes 2 : Procedure 1 and 3 can be set simultaneously because the described register is the same.
Figure 1.13.10 Setting of Programmable Waveform Generation Mode (1)
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Procedure 4 Setting timer
* when timer 1 is used Timer 1 (T1) [Address 00F416]
Timer 1 count value is set
* when timer 2 is used Timer 2 (T2) [Address 00F516]
Timer 2 count value is set
Procedure 5 Start of timer count
* when timer 1 is used
b7 b0
10 * when timer 2 is used
b7 b0
Timer 1 mode register (T1M) [Address 00F916]
Timer 1 count is started
10
Timer 2 mode register (T2M) [Address 00FA16]
Timer 2 count is started
Figure 1.13.11 Setting of Programmable Waveform Generation Mode (2)
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1.13.6 Notes on Usage Pay attention to the following notes when timer 1 or timer 2 is used. (1) In All Modes A write to an operating timer causes the contents of the timer to be affected, so that the period from the last underflow until the next underflow is undefined. In the count operation, the contents of each timer are decremented by 1 at every rising edge of the count source, while the contents of each timer are transferred to the latch for reading at the falling edge, so that the read value of the timer may be different from its real value by +1. Figure 1.13.12 shows an operation in timer 1 and timer 2 at reads.
* when `7F16' is written to timer
Count source Contents of timer 0116 0016 FF16 7E16 FF16 7D16 7C16
Timer read value Timer interrupt request bit
0216
0116
0016
7E16
7D16
Clearing by writing `0' to interrupt request bit or accepting interrupt request
Figure 1.13.12 Operations in Timer 1 and Timer 2 at Reads (2) I/O Port Pins P12 and P13 with the Alternative Functions of Timer Output Pins T0 and T1 Port pins P12 and P13 have the alternative functions of timer output pins T0 and T1 respectively. If the timer operation mode bit of the corresponding timer (1 or 2) is set to the programmable waveform generation mode, these pins cannot perform the normal function as output port pins. Refer to Figure 1.10.1 Block Diagrams of Port Pins P0i and P10-P13 in Section 1.10 Input/Output pins. Therefore, set the corresponding timer (1 or 2) operation mode bit to the timer mode when these pins are used as normal I/O port pins.
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1.14 Serial I/O
Serial I/O transmits or receives 8-bit data serially, between two microcomputers. The serial I/O of the 7480 Group and 7481 Group can operate with a transmission format of either synchronous or asynchronous (UART) type. If data is not sent on the transmission line because of collision. The microcomputer informs external the collision in the contention bus system communications by generating a bus arbitration interrupt request. 1.14.1 Registers Associated with Serial I/O Figure 1.14.1 shows the memory map of the registers associated with serial I/O.
00E016 Transmit/receive buffer register (TB/RB) 00E116 Serial I/O status register (SIOSTS) 00E216 Serial I/O control register (SIOCON) 00E316 UART control register (UARTCON) 00E416 Baud rate generator (BRG) 00E516 Bus collision detection control register (BUSARBCON)
Figure 1.14.1 Memory Map of Registers Associated with Serial I/O
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1.14 Serial I/O
(1) Transmit Buffer Register and Receive Buffer Register The transmit buffer register and the receive buffer register are located at the same address. These registers are written transmit data and read receive data when clock synchronous or clock asynchronous serial I/O is used. Clock Synchronous Serial I/O A write to the transmit buffer register (Note) starts the following operations: * When the BRG output/4 is selected as the synchronous clock, communication is started. * When an external clock is selected as the synchronous clock and the SRDY output is in the enable state, the level of the SRDY signal changes from HIGH to LOW, and the completion of the communication preparation is signaled to the external. Clock Asynchronous Serial I/O (UART) A write to the transmit buffer register (Note) starts data transmission. Note: During transmission, data is written to the transmit buffer register. During reception, dummy data is written to the transmit buffer register when the clock synchronous serial I/O is selected. Figure 1.14.2 shows the transmit/receive buffer register.
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register (TB/RB) [Address 00E016]
b 0 1 2 3 4 5 6 7
Function In transmission: Transmit data is transferred to the transmit shift register by writing transmit data. In reception: When data is stored completely in the receive shift register, the receive data is transferred to this register.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R
W
Note
Note: In transmission, this register is a write-only register. In reception, this register is a read-only register.
Figure 1.14.2 Transmit/Receive Buffer Register
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(2) Serial I/O Status Register This register consists of the flags that indicate the serial I/O transmit/receive status. Figure 1.14.3 shows the serial I/O status register.
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
1
Serial I/O status register (SIOSTS) [Address 00E116]
b 0 1 2 3 4 5 6 7
Name Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Transmit shift completion flag (TSC) Overrun error flag (OE) Parity error flag (PE) Framing error flag (FE) Summing error flag (SE) This bit is fixed to `1'.
Function 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : OE U PE U FE=0 1 : OE U PE U FE=1
At reset 0 0 0 0 0 0 0 1
R O
W
x x x x x x x x
O O O O
O O 1
Note: b4 and b5 are valid only in UART
Figure 1.14.3 Serial I/O Status Register Each flag of the serial I/O status register is described below. Transmit Buffer Empty Flag (TBE: bit 0) This flag indicates the status of the transmit buffer register. * When the data written to the transmit buffer register is transferred to the transmit shift register, this flag is set to `1'. * When transmit data is written to the transmit buffer register, this flag is cleared to `0'. This flag is valid in both clock synchronous serial I/O and UART. Receive Buffer Full Flag (RBF: bit 1) This flag indicates the status of the receive buffer register. * When receive data is stored completely in the receive shift register and transferred to the receive buffer register, this flag is set to `1'. * When the transferred data is read from the receive buffer register, this flag is cleared to `0'. This flag is valid in both clock synchronous serial I/O and UART. Transmit Shift Completion Flag (TSC: bit 2) This flag indicates the status of the transmit shift operation. * When the data in the transmit buffer register is transferred to the transmit shift register, and shift operation is started by the synchronous clock (the start bit of the transmit data is transmitted), this flag is cleared to `0'. * When the shift operation is completed (the transmission of the last bit of the transmit data is completed), this flag is set to `1'. This flag is valid in both clock synchronous serial I/O and UART.
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Overrun Error Flag (OE: bit 3) This flag indicates the status of reading receive data. * When the next receive data is stored completely in the receive shift register before the receive data stored in the receive buffer register is read through, this flag is set to `1'. * This flag is cleared to `0' by any operations listed in Table 1.14.1. This flag is valid in both clock synchronous serial I/O and UART. Parity Error Flag (PE: bit 4) This flag indicates the result of checking even or odd parity by hardware in UART. * This flag is set to `1' when the parity of the receive data differs from the predetermined parity. * This flag is cleared to `0' by any operation listed in Table 1.14.1. This flag is valid only at parity enable in UART. Framing Error Flag (FE: bit 5) This flag indicates faults of frame synchronization in UART. * When the stop bit of receive data is not received at the specified timing, this flag is set to `1'. Only the first stop bit is tested and the second stop bit is not tested. * This flag is cleared to `0' by any operation listed in Table 1.14.1. This flag is valid only in UART. Summing Error Flag (SE: bit 6) This flag indicates faults of serial I/O. * When the overrun error, parity error or framing error occurs, this flag is set to `1'. * This flag is cleared to `0' by any operation listed in Table 1.14.1. This flag is valid in both clock synchronous serial I/O and UART. [Clearing Error Flag] Error flags (bits 3 to 6) of the serial I/O status register are cleared to `0' by any operation listed in Table 1.14.1. Table 1.14.1 Clearing Error Flags Clearing Method Error Flag Overrun Error Flag Parity Error Flag Framing Error Flag Summing Error Flag Set Serial I/O Enable Bit to `0' O x x x Set Receive Enable Bit to `0' O O O O Dummy Data is Written to Serial I/O Status Register O O O O
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(3) Serial I/O Control Register This register controls the selection of a transmit/receive mode, a synchronous clock, serial I/O pin functions, etc. of serial I/O. Figure 1.14.4 shows the serial I/O control register.
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address 00E216] b 0 1 Name BRG count source selection bit (CSS) Serial I/O synchronous clock selection bit (SCS) Function 0 : f(XIN)/4 1 : f(XIN)/16
when clock synchronous serial I/O is selected
At reset 0 0
R O O
W O O
0 : BRG output/4 1 : External clock input when UART is selected 0 : BRG output/16 1 : External clock input/16 0 : P17 pin 1 : SRDY output pin 0 : Interrupt occurs when transmit
buffer is empty.
2 3
SRDY output enable bit (SRDY) Transmit interrupt source selection bit (TIC)
0 0
O O
O O
1 : Interrupt occurs when transmit shift
operation is completed.
4 5 6 7
Transmit enable bit (TE) Receive enable bit (RE) Serial I/O mode selection bit (SIOM) Serial I/O enable bit (SIOE)
0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : Asynchronous serial I/O (UART) 1 : Clock synchronous serial I/O 0 : Serial I/O disabled 1 : Serial I/O enabled
0 0 0 0
O O
O O O
O O
O
Figure 1.14.4 Serial I/O Control Register
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(4) UART Control Register This register controls the data transmission formats in clock asynchronous serial I/O (UART). This register is valid only when UART is selected. Figure 1.14.5 shows the UART control register.
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
1111
UART control register (UARTCON) [Address 00E316] b 0 1 2 3 4 5 6 7 Name Character length selection bit (CHAS) Parity enable bit (PARE) Parity selection bit (PARS) Stop bit length selection bit (STPS) These bits are fixed to `1'. 0 : 8 bits 1 : 7 bits 0 : Parity disabled 1 : Parity enabled 0 : Even parity 1 : Odd parity 0 : 1 stop bit 1 : 2 stop bits Function At reset 0 0 0 0 1 1 1 1 R O O O O 1 1 1 1 W O
O O O
x x x x
Figure 1.14.5 UART Control Register
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(5) Baud Rate Generator (BRG) The baud rate generator is an 8-bit counter with an auto-reload register, used only for serial I/O. When the serial I/O synchronous clock selection bit of the serial I/O control register is `0', setting value `n' (any number of 0016 to FF16) to the baud rate generator outputs a signal of the BRG count source (Note 1) divided by `n + 1' as the BRG output (Note 2) . Notes 1: * f(XIN)/4: when the BRG count source selection bit of the serial I/O control register is `0'. * f(XIN)/16: when the BRG count source selection bit is `1'. 2: * BRG output/4 is used for the synchronous clock in clock synchronous serial I/O. * BRG output/16 is used for the synchronous clock in clock asynchronous serial I/O. Figure 1.14.6 shows the baud rate generator.
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address 00E416]
b 0 1 2 3 4 5 6 7
Function * 8-bit timer for baud rate generation of serial I/O. * Valid only when BRG output divided by 4 or 16 is selected as synchronous clock.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R O O O O O O O O
W O O O O O O O O
Figure 1.14.6 Baud Rate Generator (6) Bus Collision Detection Control Register This register consists of the bits controlling the valid/invalid of the bus collision detection. Figure 1.14.7 shows the bus collision detection control register.
Bus collision detection control register
b7 b6 b5 b4 b3 b2 b1 b0
0000000
Bus collision detection control register (BUSARBCON) [Address 00E516] R O 0 0 0 0 0 0 0 W O
b 0 1 2 3 4 5 6 7
Name Bus collision detection enable bit
Function 0 : Collision detection invalid 1 : Collision detection valid
At reset 0 0 0 0 0 0 0 0
Not implemented. Writing to these bits is disabled. These bits are `0' at reading.
x x x x x x x
Figure 1.14.7 Bus Collision Detection Control Register
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1.14.2 Clock Synchronous Serial I/O In clock synchronous serial I/O, the transmit operation of the transmitter (Note 1) and the receive operation of the receiver (Note 2) are performed simultaneously, synchronizing with the synchronous clock used for transferring, which is generated by the clock control circuit. Notes 1: Synchronized with falling edges of the synchronous clock, data is transmitted from the TxD pin of the transmitter by the bit. 2: Synchronized with rising edges of the synchronous clock, data is received from the RxD pin of the receiver by the bit. Clock synchronous serial I/O is selected by setting the serial I/O mode selection bit of the serial I/O control register to `1'. Data Communication * Half-duplex communication: one of the two communicating microcomputers operates only as a transmitter and the other only as a receiver at a time or vice versa. * Full-duplex communication: both of the two communicating microcomputers operate simultaneously as transmitter and receiver. Synchronous Clock A synchronous clock is selected by the serial I/O synchronous clock selection bit of the serial I/O control register as follows: * 0: BRG output/4 * 1: External clock input to the SCLK pin For the BRG output, refer to (5) Baud Rate Generator (BRG) in Section 1.14.1. When a clock synchronous serial I/O communication is carried out between two microcomputers, the synchronous clock is normally selected as follows: * Microcomputer 1 clears the serial I/O synchronous clock selection bit to `0', and 8 synchronous clock pulses, generated by writing to the transmit buffer register, are output from the SCLK pin. * Microcomputer 2 selects the external clock and inputs the pulses outputted from microcomputer 1 to the SCLK pin. This is the synchronous clock. Note: When an external clock is selected as the synchronous clock: Perform the following operations while the SCLK pin input is HIGH during data transmission: * Write `1' to the transmit enable bit * Write transmit data to the transmit buffer register The shift operations of the transmit shift register and the receive shift register are performed while the synchronous clock is being input to the serial I/O circuit. Stop the synchronous clock with 8 cycles when an external clock is selected as the synchronous clock. The synchronous clock automatically stops after 8 synchronous clock pulses generated when the BRG output/4 is selected as the synchronous clock.
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Data Transfer Rate (Baud Rate) In clock synchronous serial I/O, the data transfer rate (baud rate), which is the frequency of the synchronous clock, is calculated by the following formulas:
* When the serial I/O synchronous clock selection bit is `0'. (BRG output/4 is selected as the synchronous clock) Baud rate [bps] = f(XIN) Division ratio (Note 1) x (BRG setting value (Note 2) + 1) x 4
Notes 1: BRG count source selection bit of the serial I/O control register is as follows: * `0': Division ratio is 4 * `1': Division ratio is 16. 2: The value written to the baud rate generator (0016 to FF16). * When the serial I/O synchronous clock selection bit is `1' (an external clock input is selected as the synchronous clock): Baud rate [bps] = the external clock input frequency from the SCLK pin
Output of SRDY Signal In clock synchronous serial I/O, the output level of the SRDY pin changes from HIGH to LOW by writing to the transmit buffer register when the SRDY output enable bit of serial I/O control register is `1'. The completion of the serial I/O communication preparation is signaled to the external by the SRDY output. Also, the SRDY pin returns to the HIGH state at the first falling edge of the synchronous clock. Note: Set the transmit enable bit to `1' as well as the receive enable bit and the SRDY output enable bit of the serial I/O control register when the receiver outputs the SRDY signal while the external clock is selected as the synchronous clock. Starting of Transmission and Reception * When the BRG output/4 is selected as the synchronous clock: Transmitting and receiving starts when a write to the transmit buffer register occurs. Normally, communication is started after the completion of communication preparation of the target unit is recognized with the SRDY signal. * When the external clock is selected as the synchronous clock: Transmitting and receiving starts when input to the external clock starts. When data is written to the transmit buffer register, the output level of the SRDY pin changes from HIGH to LOW and informs the target unit of the completion of communication preparation.
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(1) Block Diagram of Clock Synchronous Serial I/O Figure 1.14.8 shows the block diagram of a clock synchronous serial I/O.
Data bus P16 RxD Receive enable bit (RE) SCLK Serial I/O enable bit (SIOE) BRG count source selection bit (CSS) 1/4 1/4 SRDY output enable bit Falling edge (SRDY) F/F detection Serial I/O synchronous clock selection bit (SCS) Division ratio 1/(n + 1) Baud rate generator 1/4 Address 00E416 Clock control circuit P14 Address 00E016 Receive buffer register Receive shift register Clock control circuit Address 00E216 Serial I/O control register Receive buffer full flag (RBF) Receive interrupt request (RI)
XIN
SRDY
TxD P17
Transmit enable bit (TE) Transmit shift register
P15
Transmit buffer register Address 00E016 Data bus
Transmit interrupt source selection bit (TIC)
Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 00E116
Figure 1.14.8 Block Diagram of Clock Synchronous Serial I/O
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(2) Operations of Clock Synchronous Serial I/O Transmission Transmit Operation When transmit data is written to the transmit buffer register (Note 1), the transmit buffer empty flag of the serial I/O status register is cleared to `0'. The transmit data written to the transmit buffer register is transferred to the transmit shift register. When the data transfer to the transmit shift register is completed, the transmit buffer empty flag goes to `1' (Note 2). In this instance, when the BRG output/4 is selected as the synchronous clock, 8 synchronous clock pulses are generated. Synchronized with a falling edge of the synchronous clock, the least significant bit (LSB) of the transmit data transferred to the transmit shift register is output from the TxD pin. At this time, the contents of the transmit shift register are shifted to the low-order direction by one bit, and the transmit shift completion flag is cleared to `0'. By repeating the shift operation of `Transmit Operation ' 8 times, 8-bit transmit data is output from the TxD pin by the bit from the LSB. When 8 bits of the transmit data are output by the 8 shift operations, the transmit shift completion flag is set to `1' (Note 3). Notes 1: When the external clock is selected as the synchronous clock, write the transmit data to the transmit buffer register during the HIGH state of the synchronous clock. 2: When the transmit buffer empty flag is `1', the next transmit data can be written to the transmit buffer register. 3: The supply of the synchronous clock pulse to the transmit shift register stops automatically upon transmit completion when the BRG output/4 is selected as the synchronous clock. However, when the next transmit data is written to the transmit buffer register during the `0' state of the transmit shift completion flag, the supply of the synchronous clock pulse continues, and data is successively transmitted. When the external clock is selected as the synchronous clock, shift operation continues as long as the external clock is being input. Therefore, it is necessary to stop the external clock after transmission is completed. Serial I/O Transmit Interrupt In the following cases, the serial I/O transmit interrupt request bit of interrupt request register 1 is set to `1': then the interrupt request is generated. * When the transmit interrupt source selection bit is `0', and the data written to the transmit buffer register is transferred to the transmit shift register (`Transmit Operation '). * When the transmit interrupt source selection bit is `1', and the shift operation of the transmit shift register is completed (`Transmit Operation '). Figure 1.14.9 shows the transmit operation of clock synchronous serial I/O. The numbers in the figure corresponds to those of the above-mentioned `Transmit Operation'. Figure 1.14.10 shows a transmit timing of clock synchronous serial I/O.
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1
Data bus Writing transmit data Address 00E016 Transmit buffer register
3
Synchronous clock b0 D7 D6 D5 D4 D3 D2 D1 D0
P15/TxD
Transmit shift register Serial I/O status register Address 00E116
1 0
b0
Serial I/O status register Address 00E116
1 0
b2
Transmit buffer empty flag
Transmit shift completion flag
2
Address 00E016 Transmit buffer register Transferring transmit data Transmit shift register
4
Synchronous clock b0 D7 D6 D5 D4 D3 D2 D1
P15/TxD
Transmit shift register Serial I/O status register Address 00E116
0
5
1
b0
Synchronous clock b0 D7
Transmit buffer empty flag
Transmit shift register Serial I/O status register Address 00E116
P15/TxD
0 1
b2
Transmit shift completion flag
Figure 1.14.9 Transmit Operation of Clock Synchronous Serial I/O
Synchronous clock D0 D1 D2 D3 D4 D5 D6 D7
TxD pin Transmit buffer register write signal SRDY pin Transmit buffer empty flag
Transmit shift completion flag
(Note 1) (Note 2)
Serial I/O transmit interrupt request bit A A : Clearing by writing `0' to the serial I/O transmit interrupt request bit or accepting a serial I/O transmit interrupt request. Notes 1: When the transmit interrupt source selection bit is `0' (transmit buffer is emptied). 2: When the transmit interrupt source selection bit is `1' (transmit shift operation is completed). A
Figure 1.14.10 Transmit Timing of Clock Synchronous Serial I/O
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(3) Operations of Clock Synchronous Serial I/O Reception Receive Operation Synchronized with a rising edge of the synchronous clock, a transmitted bit data is received on the RxD pin, which is stored in the most significant bit (MSB) of the receive shift register. The contents of the receive shift register are shifted to the low-order direction by one bit every time a bit data is received, and the next bit data is stored in the MSB. 8-bit data is fully stored in the receive shift register by repeating this shift operation 8 times. The completely received 8-bit data stored in the receive shift register is transferred to the receive buffer register. When the data transfer to the receive buffer register is completed, the receive buffer full flag of the serial I/O status register is set to `1' (Note). Note: If the next data is stored completely word in the receive shift register before the data transferred from the receive shift register to the receive buffer register is read through, the overrun error is generated. At this time, the overrun error flag and the summing error flag of the serial I/O status register are set to `1'. For the handling in this case, refer to ` Handling when overrun error is generated' in (5) Notes on Usage of Clock Synchronous Serial I/O. When the receive buffer register is read, the receive buffer full flag is cleared to `0'. Serial I/O Receive Interrupt When the data stored completely in the receive shift register is transferred to the receive buffer register (`Receive Operation '), the serial I/O receive interrupt request bit of interrupt request register 1 is set to `1'; then the interrupt request is generated. Figure 1.14.11 shows the receive operation of clock synchronous serial I/O. The numbers in the figure corresponds to those of the above-mentioned `Receive Operation'. Figure 1.14.12 shows a receive timing of clock synchronous serial I/O.
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1
P14/RxD
Synchronous clock b0 D0
3
Synchronous clock
Receive shift register
Receive shift register D7 D6 D5 D4 D3 D2 D1 D0 Transferring receive data Address 00E016 Receive buffer register
2
Synchronous clock b0
P14/RxD
D3 D2 D1 D0
Serial I/O status register Address 00E116
0 1
b1
Receive shift register
Receive buffer full flag
Figure 1.14.11 Receive Operation of Clock Synchronous Serial I/O
Synchronous clock
RxD pin Transmit buffer register write signal SRDY pin
D0
D1
D2
D3
D4
D5
D6
D7
Reading to receive shift register
Receive buffer read signal
Receive buffer full flag Serial I/O receive interrupt request bit A A : Clearing by writing `0' to the serial I/O receive interrupt request bit or accepting a serial I/O receive interrupt request.
Figure 1.14.12 Receive Timing of Clock Synchronous Serial I/O
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(4) Setting of Clock Synchronous Serial I/O Figures 1.14.13 and 1.14.14 show the setting of clock synchronous serial I/O.
Procedure 1 Stop and initialization of serial I/O operation
b7 b0
00
Serial I/O control register (SIOCON) [Address 00E216] Transmit operation stop and initialized Receive operation stop and initialized
Procedure 2 Disabling serial I/O transmit/receive interrupt
b7 b0
00
Interrupt control register 1 (ICON1) [Address 00FE16] Serial I/O receive interrupt disabled Serial I/O transmit interrupt disabled
Procedure 3 Setting baud rate generator when BRG output/4 is selected as synchronous clock
Baud rate generator (BRG) [Address 00E416] Baud rate value is set
Procedure 4 Setting serial I/O control register
b7 b0
11
Serial I/O control register (SIOCON) [Address 00E216] BRG count source selection (valid only when BRG output/4 is selected as synchronous clock)
0: f(XIN)/4 1: f(XIN)/16
Serial I/O synchronous clock selection
0: BRG output/ 4 1: External clock input
SRDY output enable selection
0: P17/SRDY pin is operated as normal I/O pin 1: P17/SRDY pin is operated as SRDY pin (Note 1)
Transmit interrupt source selection (valid only when transmitting)
0: when transmit buffer is empty 1: when transmit shift operation is completed
Transmit enable selection
0: transmit disabled 1: transmit enabled (Note 2)
Receive enable selection
0: receive disabled 1: receive enabled
Clock synchronous serial I/O selected Serial I/O enabled (P14-P17 are operated as serial I/O pin)
Notes 1: When the following conditions are satisfied, set the transmit enable bit in addition to the receive enable bit and SRDY output enable bit to `1'. * Half-duplex communication is performed * External clock is selected as synchronous clock for receive side * SRDY output is performed. 2: Keep SCLK pin input HIGH when writing transmit enable bit to `1' to select the external clock input as the synchronous clock.
Figure 1.14.13 Setting of Clock Synchronous Serial I/O (1)
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Procedure 5 Setting interrupt when serial I/O transmit/receive interrupt is used (Note 3)
1. `0' is set to serial I/O transmit/receive interrupt request bit
b7 b0
00
Interrupt request register 1 (IREQ1) [Address 00FC16] Serial I/O receive interrupt request bit (when receiving) Serial I/O transmit interrupt request bit (when transmitting)
2. Serial I/O transmit/receive interrupt is enabled
b7 b0
11
Interrupt control register 1 (ICON1) [Address 00FE16] Serial I/O receive interrupt enabled (when receiving) Serial I/O transmit interrupt enabled (when transmitting)
Notes 3: Refer to Handling when overrun error is generated in (5) Notes on Usage of Clock Synchronous Serial I/O. Procedure 6 Start of data transmit/receive
Transmit buffer register (TB) [Address 00E016] Writing transmit data when transmitting (Note 4) Writing dummy data when receiving half-duplex communication
Notes 4: Keep SCLK pin input HIGH when writing transmit data to transmit buffer register to select the external clock input as the synchronous clock.
Figure 1.14.14 Setting of Clock Synchronous Serial I/O (2)
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(5) Notes on Usage of Clock Synchronous Serial I/O Pay attention to the following notes when clock synchronous serial I/O is selected. Selecting External Clock as Synchronous Clock Perform the following operations while the SCLK pin input is HIGH during transmission: * Write `1' to the transmit enable bit * Write transmit data to the transmit buffer register The shift operations of the transmit shift register and the receive shift register are performed while the synchronous clock is being input to the serial I/O circuit. Stop the synchronous clock with 8 cycles. Keep the HIGH- and the LOW- width (TWH and TWL) of the pulses used as the external clock source TWH, TWL [s] (8/f(XIN) [Hz]). For example, use a frequency of 500 kHz or less (50% duty cycle) as the external clock source when f(XIN) = 8 MHz. Set the transmit enable bit to `1' as well as the receive enable bit and the SRDY output enable bit of the serial I/O control register when the receiver outputs the SRDY signal. Handling Recovering from Errors Generated Handling when overrun error is generated If the next data is stored completely word in the receive shift register before the data transferred from the receive shift register to the receive buffer register is read through, the overrun error is generated. At this time, the overrun error flag and the summing error flag of the serial I/O status register are set to `1'. The contents of the receive shift register are not transferred to the receive buffer register, so that the contents of the receive buffer register remain unaffected. As a result, if the contents of the receive buffer register are read, the data of the receive shift register is not transferred to the receive buffer register and becomes invalid. When the overrun error occurs, clear the overrun error flag to `0' by any of the following operations, and perform receive preparation again. * Clear the serial I/O enable bit of the serial I/O control register to `0'. (In this case, only the overrun error flag returns to `0'.) * Clear the receive enable bit of the serial I/O control register to `0'. * Write dummy data into the serial I/O status register. Referring to Transmit Shift Completion Flag The transmit shift completion flag changes from `1' to `0' with a delay of 0.5 to 1.5 clocks of the synchronous clock. Therefore, pay attention to this delay when data transmission is controlled, by referring to the transmit shift completion flag after the transmit data is written to the transmit buffer register.
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Stopping Transmission/Reception of Clock Synchronous Serial I/O In order to stop the transmit operation in half-duplex transmission, clear the transmit enable bit of the serial I/O control register to `0'. As a result, the following stop and initialization of transmit operation are performed: * To stop and initialize the clock supplied to the transmit shift register * To clear the transmit shift register (Only when `0' is written to the transmit enable bit while the SCLK pin input is HIGH, selecting an external clock as the synchronous clock.) * To clear the transmit buffer empty flag and transmit shift completion flag REASON: Neither stopping transmit operation nor initializing the transmitter circuit is performed even when the serial I/O enable bit is cleared to `0' (serial I/O disabled), and internal transmit operation continues. (Because serial I/O pins TxD, RxD, SCLK, and SRDY function as I/O port pins, transmit data cannot be output to the external.) In order to stop the receive operation in half-duplex transmission, clear the receive enable bit or the serial I/O enable bit of the serial I/O control register to `0'. As a result, the following stop and initialization of the receive operation are performed: * To stop and initialize the clock supplied to the receive shift register * To clear the receive shift register * To clear every error flag * To clear the receive buffer full flag In order to stop the transmit and receive operations in full-duplex transmission, clear both the transmit enable bit and the receive enable bit of the serial I/O control register to `0' at the same time. (To stop only one of the transmit or receive operation cannot be done in the full-duplex communication of clock synchronous serial I/O.) REASON: In clock synchronous serial I/O, the same clock is used for transmission and reception. Therefore, transmission and reception cannot be synchronized when either transmit or receive operation is disabled, causing displacement of bit positions. Re-setting Serial I/O Control Register Re-set the serial I/O control register according to the following sequence: Clear both the transmit and receive enable bits of the serial I/O control register to `0' to stop and initialize transmit and receive operations. Set bits 0 to 3 and 6 of the serial I/O control register. Set the transmit enable bit or receive enable bit to `1'. (Procedures and can be performed simultaneously with the LDM instruction.)
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Using Serial I/O Transmit Interrupt and Serial I/O Receive Interrupt Set the associated registers in the following sequence to use serial I/O transmit interrupt. Clear the serial I/O transmit interrupt enable bit of interrupt control register 1 to `0'. Set the serial I/O control register. Execute one or more instructions such as NOP. Clear the serial I/O transmit interrupt request bit of interrupt request register 1 to `0'. Set the serial I/O transmit interrupt enable bit of interrupt control register 1 to `1'. REASONS 1: If normal port pins are switched to serial I/O pins with the serial I/O control register, the serial I/O transmit interrupt request bit may become `1'. 2: If the transmit enable bit of the serial I/O control register is set to `1', the transmit buffer empty flag and the transmit shift completion flag are `1'. As a result, the serial I/O transmit interrupt request bit becomes `1' regardless of the state of the transmit interrupt source selection bit of the serial I/O control register, and the interrupt request is generated. Set the associated registers in the following sequence to use serial I/O receive interrupt. Clear the serial I/O receive interrupt enable bit of interrupt control register 1 to `0'. Set the serial I/O control register. Execute one or more instructions, such as NOP. Clear the serial I/O receive interrupt request bit of interrupt request register 1 to `0'. Set the serial I/O receive interrupt enable bit of interrupt control register 1 to `1'. REASON: If normal port pins are switched to serial I/O pins with the serial I/O control register, the serial I/O receive interrupt request bit may become `1'.
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1.14.3 Clock Asynchronous Serial I/O (UART) In clock asynchronous serial I/O (UART), the transmit operation of the transmitter and the receive operation of the receiver are performed simultaneously, synchronizing with the synchronous clock used for transferring, which is generated by the clock control circuit. In UART, the transmitter and the receiver have the same transmit/receive baud rate and the same data transfer format. UART is selected by clearing the serial I/O mode selection bit of the serial I/O control register to `0'. Data Communication * Half-duplex communication: one of the two communicating microcomputers operates only as a transmitter and the other only as a receiver at a time or vice versa. * Full-duplex communication: both of the two communicating microcomputers operate simultaneously as transmitter and receiver. Synchronous Clock A synchronous clock is selected by the serial I/O synchronous clock selection bit of the serial I/O control register as follows: * 0: BRG output /16 * 1: External clock/16 input to the SCLK pin For the BRG output, refer to (5) Baud Rate Generator in Section 1.14.1. Notes 1: In UART, the P16/SCLK pin can be used as port pin P16 when the BRG output/16 is selected as the synchronous clock, since the SCLK pin is not used to output the synchronous clock to the external. 2: When the external clock/16 is selected as a synchronous clock, keep the HIGH- and the LOWwidth (TWH and TWL) of the pulses used as the external clock source TWH, TWL [s] (2/f(XIN) [Hz]). For example, use a frequency of 2 MHz or less (50% duty cycle) as the external clock source when f(XIN) = 8 MHz.
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Data Transfer Rate (Baud Rate) In UART, the baud rate, which is the frequency of the synchronous clock, is calculated by the following formulas. * When the serial I/O synchronous clock selection bit is `0':. (BRG output/16 is selected as the synchronous clock.) Baud rate [bps] = f(XIN) Division ratio (Note 1) x (BRG setting value (Note 2) + 1) x 16
Notes 1: BRG count source selection bit of the serial I/O control register is as follows: * `0': Division ratio is 4 * `1': Division ratio is 16. 2: The value written to the baud rate generator (0016 to FF16). * When the serial I/O synchronous clock selection bit is `1' (the external clock/16 input is selected as the synchronous clock): Baud rate [bps] = External clock input frequency from the SCLK pin 16
Table 1.14.2 lists an example of baud rates. Table 1.14.2 Example of Baud Rates Baud Rate [bps] 300 600 1200 2400 4800 9600 15600 31200 41600 f(XIN) = 7.9872 MHz BRG Setting Value Count Source f(XIN)/16 f(XIN)/16 f(XIN)/16 f(XIN)/16 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 f(XIN)/4 103 (6716) 51 (3316) 25 (1916) 12 (0C16) 25 (1916) 12 (0C16) 7 (0716) 3 (0316) 2 (0216) f(XIN) = 3.9936 MHz Count Source BRG Setting Value f(XIN)/16 51 (3316) f(XIN)/16 f(XIN)/16 f(XIN)/4 f(XIN)/4 25 (1916) 12 (0C16) 25 (1916) 12 (0C16)
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Data Transfer Formats In UART, the data transfer formats shown in Figure 1.14.15 can be selected with the UART control register.
LSB
MSB
* 1ST - 8DATA - 1SP * 1ST - 8DATA - 2SP * 1ST - 8DATA - 1PA - 1SP * 1ST - 8DATA - 1PA - 2SP * 1ST - 7DATA - 1SP * 1ST - 7DATA - 2SP * 1ST - 7DATA - 1PA - 1SP * 1ST - 7DATA - 1PA - 2SP
ST ST ST ST ST ST ST ST
D0
LSB
D1 D1 D1 D1 D1 D1 D1 D1
D2 D2 D2 D2 D2 D2 D2 D2
D3 D3 D3 D3 D3 D3 D3 D3
D4 D4 D4 D4 D4 D4 D4 D4
D5 D5 D5 D5 D5 D5 D5 D5
D6 D6 D6 D6
MSB
D7
MSB
SP SP PA PA SP SP SP SP
D0
LSB
D7
MSB
D0
LSB
D7
MSB
D0
LSB
D7 SP SP PA PA
D0
LSB
D6
MSB
D0
LSB
D6
MSB
SP SP SP SP
D0
LSB
D6
MSB
D0
D6
ST: Start bit Di(i = 0 to 7): Data bit PA: Parity bit SP: Stop bit
Figure 1.14.15 Data Transfer Formats in UART Table 1.14.3 lists the setting of the UART control register, and Table 1.14.4 lists the function of the UART data transfer bits. Table 1.14.3 Setting of UART Control Register Transfer Data Format 1ST--8DATA--1SP 1ST--7DATA--1SP 1ST--8DATA--1PA--1SP 1ST--7DATA--1PA--1SP 1ST--8DATA--2SP 1ST--7DATA--2SP 1ST--8DATA--1PA--2SP 1ST--7DATA--1PA--2SP Notes 1: Stop bit length selection bit 2: Parity selection bit 3: Parity enable bit 4: Character length selection bit b3 (Note 1) 0 0 0 0 1 1 1 1 UART Control Register b2 (Note 2) b1 (Note 3) -- 0: Even parity 1: Odd parity -- 0: Even parity 1: Odd parity 0 0 1 1 0 0 1 1 b0 (Note 4) 0 1 0 1 0 1 0 1
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Table 1.14.4 Function of UART Transfer Data Bits Name Start Bit (ST) Data Bits (DATA) Parity Bit (PA) Stop Bit(s) (SP)
Function
Indicates the start of data transmission. The LOW signal of one-bit wide is added to the head of the transmit data. The transmit data written into UART transmit buffer register. Data `0' represents LOW, and `1' the HIGH signal. Added to the end of the data bits to enhance the reliability of communications. The number of `1' in transmit/receive data including parity bit keeps even or odd according to the setting value of parity selection bit. Added to the end of the data bits (or after the parity bit if parity is valid) and indicates the transmission is completed. The HIGH signal of one or two bits wide is output as stop bit.
(1) Block Diagram of UART Figure 1.14.16 shows the block diagram of UART.
Data bus RxD P14 Receive enable bit (RE) Overrun error ST detection flag(OE) 7 bits Character length 8 bits selection bit (CHAS) Address 00E216 Serial I/O control register Address 00E016 Receive buffer register Receive buffer full flag (RBF) Receive interrupt request (RI) Receive shift register SP detection 1/16
Address 00E316 UART control register
Parity error flag (PE) Framing error flag (FE) Clock control circuit Serial I/O enable bit(SIOE) Serial I/O synchronous clock selection bit (SCS) SCLK XIN 1/4 BRG count source selection bit (CSS) 1/4 Transmit enable bit (TE) TxD P16 P15 Division ratio 1/(n + 1) Baud rate generator Address 00E416 ST/SP/PA generation 1/16
Serial I/O synchronous clock selection bit (SCS)
Transmit shift register Transmit buffer register Address 00E016 Transmit interrupt source selection bit (TIC)
Transmit shift completion flag (TSC) Transmit interrupt request (TI) Transmit buffer empty flag (TBE) Serial I/O status register Address 00E116
Character length selection bit (CHAS)
Data bus
Figure 1.14.16 Block Diagram of UART
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(2) Operations of UART Transmission Transmit Operation When transmit data is written to the transmit buffer register, the transmit buffer empty flag of the serial I/O status register is cleared to `0'. The transmit data written to the transmit buffer register is transferred to the transmit shift register. When the data transfer to the transmit shift register is completed, the transmit buffer empty flag goes to `1' (Note 1). Synchronized with a falling edge of the synchronous clock, the start bit (the LOW level) is output from the TxD pin. Synchronized with the next falling edge of the synchronous clock, the least significant bit (LSB) of the transmit data transferred to the transmit shift register is output from the TxD pin. At this time, the contents of the transmit shift register are shifted to the low-order direction by one bit, and the serial I/O transmit shift completion flag is cleared to `0'. By repeating the shift operation of `Transmit Operation ' `n' times (`n': the number of bits set by the character length selection bit of the UART control register), the transmit data is output from the TxD pin by the bit from the LSB. After the transmit data is output, the parity bit, and then the stop bit (the HIGH level), are output from the TxD pin synchronized with falling edges of the synchronous clock. The parity bit and the stop bit are generated and output automatically, according to the setting of the parity enable bit, the parity selection bit, and the stop bit length selection bit of the UART control register. When the last stop bit of the transfer format is output, the transmit shift completion flag is set to `1' at the next rising edge of the synchronous clock (Note 2). Notes 1: When the transmit buffer empty flag is `1', the next transmit data can be written to the transmit buffer register. 2: The supply of the synchronous clock pulse to the transmit shift register stops automatically upon transmit completion when the BRG output/16 is selected as the synchronous clock. However, when the next transmit data is written to the transmit buffer register during the `0' state of the transmit shift completion flag, the supply of the synchronous clock pulse continues, and data is successively transmitted. Serial I/O Transmit Interrupt In the following cases, the serial I/O transmit interrupt request bit of interrupt request register 1 is set to `1'; then the interrupt request is generated: * When the transmit interrupt source selection bit is `0', and the data written to the transmit buffer register is transferred to the transmit shift register (`Transmit Operation '). * When the transmit interrupt source selection bit is `1', and the shift operation of the transmit shift register is completed (`Transmit Operation '). Figure 1.14.17 shows the transmit operation of UART, and Figure 1.14.18 shows a transmit timing example in UART.
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1
Data bus Writing transmit data Address 00E016 Transmit buffer register
4
Synchronous clock b0 D7 D6 D5 D4 D3 D2 D1 D0
Transmit shift register Serial I/O status register Address 00E116
P15/TxD
1 0
Serial I/O status register Address 00E116
1 0
Transmit buffer empty flag
b0
Transmit shift completion flag
b2
2
Address 00E016 Transmit buffer register Transferring transmit data Transmit shift register
5
Synchronous clock b0 D7 D6 D5 D4 D3 D2 D1
Transmit shift register Serial I/O status register Address 00E116
P15/TxD
0 1
b0
6
Synchronous clock
Transmit buffer empty flag
SP
P15/TxD
3
Synchronous clock b0 D7 D6 D5 D4 D3 D2 D1 D0 ST
Serial I/O status register Address 00E116 P15/TxD
0 1
b2
Transmit shift register
Transmit shift completion flag
Figure 1.14.17 Transmit Operation of UART
* Example of 1ST-8DATA-1SP
Synchronous clock ST D0 D1 D2 D6 D7 SP
TxD pin Transmit buffer register write signal Transmit buffer empty flag
Transmit shift completion flag
(Note 1) (Note 2)
Serial I/O transmit interrupt request bit A A : Clearing by writing `0' to the serial I/O transmit interrupt request bit or accepting a serial I/O transmit interrupt request. Notes 1: When the transmit interrupt source selection bit is `0' (transmit buffer is emptied). 2: When the transmit interrupt source selection bit is `1' (transmit shift operation is completed). A
Figure 1.14.18 Transmit Timing example in UART
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(3) Operations of UART Reception Receive Operation When a falling edge of the RxD pin input is detected, this input level to the RxD pin is identified according to the subsequent rising edge of the synchronous clock as follows: * As the start bit when the level is LOW. * As noise when the level is HIGH. In this case, the CPU suspends the receive operation and enters the waiting state for the next start bit. Synchronized with the rising edge of the synchronous clock, transmitted data is received on the RxD pin by the bit and stored in the most significant bit (MSB) of the receive shift register. Every time a data bit is received, the contents of the receive shift register are shifted by one bit to the low-order direction. The receive shift operation of `Receive Operation ' is performed `n' times (`n': the number of bits set by the character length selection bit of the UART control register), and the received data is stored completely in the receive shift register (Note 1). The received data stored completely in the receive shift register is transferred to the receive buffer register. The parity bit and the stop bit are input to the RxD pin synchronized with rising edges of the synchronous clock. When the last stop bit (the HIGH level) is input to the RxD pin, the receive buffer full flag of the serial I/O status register is set to `1' at the subsequent falling edge of the synchronous clock (Note 2). At this time, error flags are checked. Notes 1: When the character length selection bit is `1' (7 bits wide), the MSB of the receive buffer register becomes `0'. 2: If the next data is stored completely in the receive shift register before the data transferred from the receive shift register to the receive buffer register is read through (the receive buffer full flag is `1'), the overrun error is generated. At this time, the overrun error flag and the summing error flag of the serial I/O status register is set to `1'. Refer to (5) Notes on Usage of UART. When the receive buffer register is read, the receive buffer full flag is cleared to `0'. Serial I/O Receive Interrupt When the receive buffer full flag goes to `1' (`Receive Operation '), the serial I/O receive interrupt request bit of interrupt request register 1 is set to `1'; then the interrupt request is generated. Figure 1.14.19 shows the receive operation of UART and Figure 1.14.20 shows a receive timing example in UART.
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1
Synchronous clock
RxD (Noise) RxD (ST) HIGH is identified as noise. LOW is identified as a start bit. Serial I/O status register Address 00E116
5
Synchronous clock
RxD (SP) Stop bit detected
0000
0 1
b1

b6 b5 b4 b3
2
Synchronous clock
b0
Receive buffer full flag
P14/RxD
D0
Receive shift register
3
P14/RxD
Synchronous clock
b0 D3 D2 D1 D0
Receive shift register
: b3
b4 b5 b6
*** *** *** ***
Overrun error flag (OE); set to `1' when overrun error occurs. Parity error flag (PE); set to `1' when parity error occurs. Framing error flag (FE); set to `1' when framing error occurs. Summing error flag (SE); set to `1' when OE U PE U FE = 1.
4
Synchronous clock Receive shift register D7 D6 D5 D4 D3 D2 D1 D0 Receive data transfer Address 00E016 Receive buffer register
Figure 1.14.19 Receive Operation of UART
* Example of 1ST-7DATA-1PA-1SP
Synchronous clock ST
Test whether a start bit or not
RxD pin Receive buffer register read signal Receive buffer full flag
D0
D1
D2
D6
PA
SP
Reading to the receive shift register
Serial I/O receive interrupt request bit A A : Clearing by writing `0' to the serial I/O receive interrupt request bit or accepting a serial I/O receive interrupt request.
Figure 1.14.20 Receive Timing Example in UART
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(4) Setting of UART Figures 1.14.21 and 1.14.22 show the setting of UART.
Procedure 1 Stop of serial I/O operation and initialization
b7 b0
00
Serial I/O control register (SIOCON) [Address 00E216] Transmission operation stop and initialized Receive operation stop and initialized
Procedure 2 Disabling serial I/O transmit/receive interrupt
b7 b0
00
Interrupt control register 1 (ICON1) [Address 00FE16] Serial I/O receive interrupt disabled Serial I/O transmit interrupt disabled
Procedure 3 Setting baud rate generator when BRG output/16 is selected as synchronous clock
Baud rate generator (BRG) [Address 00E416] Baud rate value is set
Procedure 4 Setting serial I/O control register
b7 b0
10
X
Serial I/O control register (SIOCON) [Address 00E216] BRG count source selection (valid only when BRG output/16 is selected as synchronous clock)
0: f(XIN)/4 1: f(XIN)/16
Serial I/O synchronous clock selection
0: BRG output/16 (Note 1) 1: External clock input/16
This bit is invalid when UART is selected. Transmit interrupt source selection (valid only when transmitting)
0: when transmit buffer is empty 1: when transmit shift operation is completed
Transmit enable selection
0: transmit disabled 1: transmit enabled
Receive enable selection
0: receive disabled 1: receive enabled
Clock asynchronous serial I/O (UART) selected Serial I/O enabled (P14-P16 are operated as serial I/O pin)
Notes 1: When BRG output/16 is selected as the synchronous clock, P16/SCLK pin can be used as port pin P16 because the synchronous clock is not output externally from SCLK pin.
Figure 1.14.21 Setting of UART (1)
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Procedure 5 Setting UART control register
b7 b0
UART control register (UARTCON) [Address 00E316] Character length selection 0: 8 bits 1: 7 bits Parity enable selection 0: Parity disabled 1: Parity enabled Parity selection (valid only when parity enabled) 0: Even parity 1: Odd parity Stop bit length selection 0: 1 stop bit 1: 2 stop bits
Procedure 6 Setting interrupt when serial I/O transmit/receive interrupt is used (Note 2)
1. `0' is set to serial I/O transmit/receive interrupt request bit
b7 b0
00
Interrupt request register 1 (IREQ1) [Address 00FC16] Serial I/O receive interrupt request bit (when receiving) Serial I/O transmit interrupt request bit (when transmitting)
2. Serial I/O transmit/receive interrupt is enabled
b7 b0
11
Interrupt control register 1 (ICON1) [Address 00FE16] Serial I/O receive interrupt enabled (when receiving) Serial I/O transmit interrupt enabled (when transmitting)
Notes 2: Refer to Using Serial I/O Transmit Interrupt and Serial I/O Receive Interrupt in (5) Notes on Usage of UART.
Procedure 7 Start of data transmit when transmitting
Transmit buffer register (TB) [Address 00E016] Writing transmit data
Figure 1.14.22 Setting of UART (2)
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(5) Notes on Usage of UART Pay attention to the following notes when UART is selected. Selecting BRG output/16 as Synchronous Clock Since the SCLK pin is not used to output the synchronous clock to the external, the P16/SCLK pin can be used as normal port pin P16. Selecting External Clock/16 Input as Synchronous Clock Keep the HIGH- and the LOW- width (TWH and TWL) of the pulses used as the external clock source TWH, TWL [s] (2/f(XIN) [Hz]). For example, use a frequency of 2 MHz or less (50% duty cycle) as the external clock source when f(XIN) = 8 MHz. Handling Recovering from Errors Generated Handling when parity error or framing error is generated When the parity error or the framing error occurs, the flag corresponding to each error and the summing error flag of the serial I/O status register are set to `1'. To clear these flags to `0', perform either of the following operations. * Clear the receive enable bit of the serial I/O control register to `0'. * Write dummy data to the serial I/O status register. Handling when overrun error is generated If the next data is stored completely in the receive shift register before the data transferred from the receive shift register to the receive buffer register is read through, the overrun error is generated. At this time, the overrun error flag and the summing error flag of the serial I/O status register are set to `1'. The contents of the receive shift register are not transferred to the receive buffer register, so that the contents of the receive buffer register remain unaffected. As a result, if the contents of the receive buffer register are read, the data of the receive shift register is not transferred to the receive buffer register and becomes invalid. When the overrun error occurs, clear the overrun error flag to `0' by any of the following operations and perform receive preparation again. * Clear the serial I/O enable bit of the serial I/O control register to `0'. (In this case, only the overrun error flag returns to `0'.) * Clear the receive enable bit of the serial I/O control register to `0'. * Write dummy data into the serial I/O status register. Referring to Transmit Shift Completion Flag The transmit shift completion flag changes from `1' to `0' with a delay of 0.5 to 1.5 clocks of the synchronous clock. Therefore, pay attention to this delay when data transmission is controlled, by referring to the transmit shift completion flag after the transmit data is written to the transmit buffer register.
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Stopping Transmission/Reception of UART In order to stop the transmit operation of UART, clear the transmit enable bit of the serial I/O control register to `0'. As a result, the following stop and initialization of transmit operation are performed: * To stop and initialize the clock supplied to the transmit shift register * To clear the transmit shift register. * To clear the transmit buffer empty flag and transmit shift completion flag In order to stop the receive operation of UART, clear the receive enable bit or the serial I/O enable bit of the serial I/O control register to `0'. As a result, the following stop and initialization of the receive operation are performed: * To stop and initialize the clock supplied to the receive shift register * To clear the receive shift register * To clear every error flag * To clear the receive buffer full flag Re-setting Serial I/O Control Register Re-set the serial I/O control register according to the following sequence to stop and initialize transmit and receive operations: Clear both of the transmit and receive enable bits of the serial I/O control register to `0'. Set bits 0 to 3 and 6 of the serial I/O control register. Set both the transmit and receive enable bits to `1'. (Procedures and can be performed simultaneously with the LDM instruction.) Using Serial I/O Transmit Interrupt and Serial I/O Receive Interrupt Set the associated registers in the following sequence to use serial I/O transmit interrupt. Clear the serial I/O transmit interrupt enable bit of interrupt control register 1 to `0'. Set the serial I/O control register. Execute one or more instructions such as NOP. Clear the serial I/O transmit interrupt request bit of interrupt request register 1 to `0'. Set the serial I/O transmit interrupt enable bit of interrupt control register 1 to `1'. REASONS 1: If normal port pins are switched to serial I/O pins with the serial I/O control register, the serial I/O transmit interrupt request bit may become `1'. 2: If the transmit enable bit of the serial I/O control register is set to `1', the transmit buffer empty flag and the transmit shift completion flag are `1'. As a result, the serial I/O transmit interrupt request bit becomes `1' regardless of the state of the transmit interrupt source selection bit of the serial I/O control register, and the interrupt request is generated. Set the associated registers in the following sequence to use serial I/O receive interrupt. Clear the serial I/O receive interrupt enable bit of interrupt control register 1 to `0'. Set the serial I/O control register. Execute one or more instructions, such as NOP. Clear the serial I/O receive interrupt request bit of interrupt request register 1 to `0'. Set the serial I/O receive interrupt enable bit of interrupt control register 1 to `1'. REASON: If normal port pins are switched to serial I/O pins with the serial I/O control register, the serial I/O receive interrupt request bit may become `1'.
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1.14.4 Bus Arbitration In the serial I/O communications of the contention bus system shown in Figure 1.14.23, transmit data may not correctly be sent on the transmission line because of bus collision. In the 7480 Group and 7481 Group, if the comparison of the level of serial I/O transmit pin TxD with that of serial I/O receive pin RxD results in a mismatch, the bus arbitration interrupt request is generated. This indicates that the bus collision occurred. When the bus collision detection enable bit of the bus collision detection control register is set to `1', bus collision detection can be performed. In addition, bus collision detection is valid when any of the following conditions is selected: Serial I/O mode * Clock synchronous serial I/O * Clock asynchronous serial I/O (UART) Synchronous clock * BRG output divided * External clock (or external clock/16)
LAN data bus
TxD RxD
Interface Driver/ Receiver
7480 Group 7481Group
Figure 1.14.23 Contention bus system communications
(1) Block Diagram Figure 1.14.24 shows the block diagram of the bus arbitration interrupt.
TxD pin RxD pin
D
Q
Bus arbitration interrupt request
Synchronous clock Bus collision detection enable bit Transmit enable bit
Figure 1.14.24 Block Diagram of Bus Arbitration Interrupt
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(2) Operations of Bus Arbitration Operations of bus arbitration in the serial I/O communications are described below. Bus Collision Detection The level of serial I/O transmit pin TxD is compared with that of serial I/O receive pin RxD, synchronized with rising edges of the synchronous clock which is used in serial I/O communications. * The level of 8-bit transmit data is referred for comparison in clock synchronous serial I/O. * The levels of all transmitted bits, from the start to the stop bits, are referred for comparison in UART. Bus Arbitration Interrupt When a mismatch results from the comparison of the level of the TxD pin with that of the RxD pin in bus collision detection, the bus arbitration interrupt request bit of interrupt request register 1 is set to `1'; then the interrupt request is generated. Figure 1.14.25 shows a timing of bus collision detection.
Synchronous clock
TxD pin
RxD pin
Bus arbitration interrupt request bit
Bus arbitration A : Clearing by writing `0' to the bus arbitration interrupt request bit or accepting a bus arbitration interrupt request. A
Figure 1.14.25 Timing of Bus Collision Detection
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(3) Setting of Bus Arbitration Interrupt Figure 1.14.26 shows the setting of bus arbitration interrupt.
Procedure 1 Disabling of the acceptance of the interrupts associated serial I/O
b7 b0
000
Interrupt control register 1 (ICON1) [Address 00FE16]
Serial I/O receive interrupt disabled Serial I/O transmit interrupt disabled Bus arbitration interrupt disabled
Procedure 2 Setting serial I/O full-duplex communication
1. Set Baud Rate Generator when the divided BRG output/4 or 16 is selected as the synchronous clock. 2. Set Serial I/O Control Register (in full-duplex communication). 3. Set UART Control Register (in UART).
Procedure 3 Setting bus collision detection control register
b7 b0
1
Bus collision detection control register (BUSARBCON) [Address 00E516]
Bus collision detect enabled
Procedure 4 Setting the using interrupt request bit to `0'
b7 b0
000
Interrupt request register 1 (IREQ1) [Address 00FC16]
There is no serial I/O receive interrupt request There is no serial I/O transmit interrupt request There is no bus arbitration interrupt request
Procedure 5 Enabling the acceptance of the using interrupts
b7 b0
111
Interrupt control register 1 (ICON1) [Address 00FE16]
Serial I/O receive interrupt enabled Serial I/O transmit interrupt enabled Bus arbitration interrupt enabled
Procedure 6 Writing transmit data into transmit buffer register
Figure 1.14.26 Setting of Bus Arbitration Interrupt
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1.15 A-D Converter
The 7480 Group and 7481 Group have a built-in A-D converter with: * analog input pins ...................... 8 channels (alternative functions of port P2) (Note), and * conversion system .................... 8-bit successive comparison. When the A-D converter is not used, power dissipation can be reduced by clearing the VREF connection selection bit of the A-D control register to `0' and switching off VREF. Note: In the 7480 Group, 4-channel analog input pins are implemented. 1.15.1 Block Diagram of A-D Converter Figure 1.15.1 shows the block diagram of the A-D converter.
Data bus
b4
b0
A-D control register (Address 00D916)
A-D control circuit P20/IN0 P21/IN1 P22/IN2 P23/IN3 P24/IN4 P25/IN5
(Note 2) Comparator
A-D conversion completion interrupt request
Channel selector
A-D conversion register (Address 00DA16)
Switch tree
P26/IN6 P27/IN7
Ladder resistor
VSS
(Note 1)
VREF
Notes 1: AVSS for the 44P6N package of the 7481 Group. 2: Port pins P24/IN4-P27/IN7 are not implemented in the 7480 Group.
Figure 1.15.1 Block Diagram of A-D Converter
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1.15.2 Registers Associated with A-D Converter Figure 1.15.2 shows the memory map of the registers associated with the A-D converter.
00D916 A-D control register (ADCON) 00DA16 A-D conversion register (AD)
Figure 1.15.2 Memory Map of Registers Associated with A-D Converter (1) A-D Control Register The A-D control register consists of the bits controlling the A-D converter. Figure 1.15.3 shows the A-D control register.
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address 00D916]
b 0
Name Analog input pin selection bits
b2 b1 b0
Function 0 0 0 : P20/IN0 0 0 1 : P21/IN1 0 1 0 : P22/IN2 0 1 1 : P23/IN3 1 0 0 : P24/IN4 1 0 1 : P25/IN5 1 1 0 : P26/IN6 1 1 1 : P27/IN7
At reset 0
R O
W O
1
0 (Note) 0
O
O
2
O
O
3 4
A-D conversion completion bit VREF connection selection bit
0 : Conversion in progress 1 : Conversion completed
0 : Disconnect between VREF pin and ladder resistor 1 : Connect between VREF pin and ladder resistor
1 0
O O
O
5 6 7
Not implemented. Writing to these bits is disabled. These bits are undefined at reading.
Undefined Undefined Undefined
Undefined Undefined Undefined
x x x
: The bit can be set to `0' by software, but cannot be set to `1'.
Note: Do not perform setting in the 7480 Group.
Figure 1.15.3 A-D Control Register
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(2) A-D Conversion Register This is a read-only register in which an A-D conversion result is stored. Figure 1.15.4 shows the A-D conversion register.
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address 00DA16]
b 0 1 2 3 4 5 6 7
Function Read-only register to store the A-D conversion result.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R O O O O O O O O
W
x x x x x x x x
Figure 1.15.4 A-D Conversion Register
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1.15.3 Operations of A-D Converter The A-D conversion system of the 7480 Group and 7481 Group is successive comparison conversion. The comparison result of internally generated comparison voltage Vref with input voltage VIN from an analog input pin is stored in the A-D conversion register. The operations of the A-D converter are described below. Start of A-D Conversion When the A-D conversion completion bit of the A-D control register is cleared to `0', A-D conversion is started. A-D Conversion The A-D conversion register goes to `0016'. Analog input voltage VIN is compared with comparison voltage Vref 8 times. The contents of the A-D conversion register are determined by the bit from the MSB, each time a comparison is performed. Comparison voltage Vref is determined by the following formula depending on the contents of the AD conversion register and reference voltage VREF, which is input from the VREF pin. Expression of comparison voltage Vref Vref = 0 ........................................when n = 0 VREF x (n - 0.5) ........... when n = 1 to 255 256 VREF: Reference voltage input from the VREF pin n : The contents of the A-D conversion register The first comparison (determination of bit 7 of A-D conversion register) Bit 7 of the A-D conversion register is set to `1', and comparison voltage Vref obtained by the above formula is input to the comparator. Vref is compared with VIN, and bit 7 of the A-D conversion register is determined, depending on the result of the comparison as follows: * Bit 7 remains `1' (retention) if Vref < VIN. * Bit 7 is converted to `0' if Vref > VIN. Comparison from the second time (determination of bits 6 to 0 of A-D conversion register) Every bit of bits 6 to 0 of the A-D conversion register is successively determined as bit 7 is done in the first time. (The next bit to be determined is set to `1', and the value of the bit is determined by the comparison result of VIN with Vref.) Figure 1.15.5 shows the change of the A-D conversion register and the comparison voltage during A-D conversion. A-D conversion is completed when comparison voltage Vref is compared with analog input voltage VIN 8 times and all bits of the A-D conversion register are determined. At this time, the A-D conversion completion bit of the A-D control register becomes `1'.
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The contents of A-D conversion register At A-D conversion start
Comparison voltage (Vref) [V]
00000000 10000000
VREF
2
0
- VREF
512
At the first comparison start At the second comparison start At the third comparison start
1
1000000 100000 1
VREF
2
VREF
4
-
VREF
512
12
VREF VREF VREF VREF - 512 2 4 8 VREF VREF VREF 2 4 8
....... .....
At the eighth comparison start
1234567
VREF - VREF 256 512
At A-D conversion completed (at the eighth conversion completed)
12345678
The digital value corresponding to analog input voltage
m
: The determined value obtained by m m-th (m=1 to 8) comparison result the
Figure 1.15.5 Change of A-D Conversion Register and Comparison Voltage during A-D Conversion A-D conversion interrupt When A-D conversion is completed, the A-D conversion completion interrupt request bit of interrupt request register 1 is set to `1'; then an A-D conversion completion interrupt request is generated. Reads from A-D conversion register When A-D conversion is completed, the A-D conversion register is read to obtain the A-D conversion result. The completion of A-D conversion can be acknowledged by any of the following conditions: * The A-D conversion completion bit is `1'. * The A-D conversion completion interrupt request bit is `1'. * The branch to A-D conversion completion interrupt service routine occurs (when A-D conversion completion interrupt enabled). Note: Do not read from the A-D conversion register during A-D conversion operation. A-D conversion time A-D conversion ends in 50 cycles after its start. Because the A-D converter uses the clock input divided by 2, f(XIN)/2, as the operating clock, A-D conversion time is fundamentally obtained by the following formula: A-D conversion time = 2 f(XIN) x conversion cycles (50 cycles) (12.5 s at f(XIN) = 8 MHz)
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1.15.4 Setting of A-D Conversion Figure 1.15.6 shows the setting of A-D conversion.
Procedure 1 Disabling acceptance of A-D conversion completion interrupt
b7 b0
0
Interrupt control register 1 (ICON1) [Address 00FE16] A-D conversion completion interrupt acceptance disabled
Procedure 2 Setting A-D control register
b7 b0
1
A-D control register (ADCON) [Address 00D916]
Analog input pin selection 000: P20/IN0 001: P21/IN1 010: P22/IN2 011: P23/IN3 100: P24/IN4 101: P25/IN5 110: P26/IN6 (Note 1) 111: P27/IN7
VREF and ladder resistor connected
Procedure 3 Setting A-D conversion completion interrupt request bit to `0'
b7 b0
0
Interrupt request register 1 (IREQ1) [Address 00FC16]
There is no A-D conversion completion interrupt request.
Procedure 4 Enabling acceptance of interrupt when A-D conversion interrupt is used
b7 b0
1
Interrupt control register 1 (ICON1) [Address 00FE16] A-D conversion completion interrupt acceptance enabled
Procedure 5 Start of A-D conversion (Note 2)
b7 b0
0
A-D control register (ADCON) [Address 00D916] A-D conversion start Notes 1: Do not set these bits in the 7480 Group. 2: Start A-D conversion after the following: the ladder resistor is connected to VREF pin VREF stabilization time elapses 1.0 s or more.
Figure 1.15.6 Setting of A-D Conversion
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1.15 A-D Converter
1.15.5 Notes on Usage Pay attention to the following notes when the A-D converter is used. The comparator consists of a capacitive coupling circuit, so that low clock input frequencies cause electric charge to be lost. * Use 1 MHz or more of f(XIN) during A-D conversion is performed. * Do not execute the STP instruction during A-D conversion. Voltages to be applied to the reference voltage input pin are as follows: * VREF = 2 to VCC [V] when VCC = 2.7 V to 4.0 V * VREF = 0.5 VCC to VCC [V] when VCC = 4.0 V to 5.5 V When the A-D converter is not used, connect VREF pin to the VCC pin. Apply the same voltage as to the VSS pin to analog power source voltage input pin AVSS. (The AVSS pin is dedicated to the 44P6N-A package in the 7481 Group.) Even when A-D conversion is started, the A-D conversion completion interrupt request bit is not automatically cleared to `0'. Clear this bit to `0' before A-D conversion starts. A-D conversion resumes when `0' is written into the A-D conversion completion bit of the A-D control register during A-D conversion. To start A-D conversion, set the VREF connection selection bit of the A-D control register to `1' to connect ladder resistor and the VREF. A-D conversion can then be started, after the VREF stabilization time elapses 1.0 s or more.
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1.15 A-D Converter
Figure 1.15.7 shows the internal equivalent circuit of analog input circuit. In order to perform the A-D conversion correctly, complete the charge to the internal capacitor by the specified time. The maximum output impedance of analog input source to complete the charge to the internal capacitor by this specified time is shown below. About 10 k (at f(XIN) = 8 MHz) When the maximum value of output impedance is over the above value, take countermeasures, for example, connect a capacitor (0.1 F to 1 F) between analog input pins and VSS.
VCC
(Note 2)
P2i/INi pin (i=0 to 7) (Note 1)
C1 = 10pF 50%
R(about 6 )
C2 (about 3 pF)
SW1(Note 3)
(Note 2)
SW2 Amplifier
VSS
VSS Reference voltage generation circuit Switch tree Ladder resistor
VREF switch
VSS
VREF
Notes 1: In the 7480 Group, i = 0 to 3. 2: This is a parasitic diode of output transistor. 3: SW1 is turned on only when analog input pin is selected.
Figure 1.15.7 Internal equivalent circuit of analog input circuit
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1.16 Watchdog Timer
1.16 Watchdog Timer
If a program cannot run a normal loop by a runaway, etc., the watchdog timer provides the means of returning the CPU to the reset state. In the 7480 Group and 7481 Group, invalidating the STP and WIT instructions causes a runaway to be detected more effectively. For the selection of the valid/invalid of the STP and WIT instructions, refer to Section 1.19 Power Saving Function. The watchdog timer is comprised of 7-bit watchdog timer L and 8-bit watchdog timer H (address 00FE16). 1.16.1 Block Diagram of Watchdog Timer Figure 1.16.1 shows the block diagram of the watchdog timer.
Data bus
`7F16' is set when writing to watchdog timer H 1/8 XIN `0'
`FF16' is set when writing to watchdog timer H
1/16 `1' Watchdog timer L count source selection bit
Watchdog timer L (7 bits)
Watchdog timer H (8 bits)
bit 7
RESET
Reset circuit
Internal reset
Figure 1.16.1 Block Diagram of Watchdog Timer 1.16.2 Registers Associated with Watchdog Timer Figure 1.16.2 shows the memory map of the registers associated with the watchdog timer.
00EF16
Watchdog timer H (WDTH)
00FB16
CPU mode register (CPUM)
Figure 1.16.2 Memory Map of Registers Associated with Watchdog Timer
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1.16 Watchdog Timer
(1) Watchdog Timer H Watchdog timer H indicates the high-order 8 bits of the count value of the watchdog timer. Figure 1.16.3 shows the watchdog timer H.
Watchdog timer H
b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer H (WDTH) [Address 00EF16]
b 0 1 2 3 4 5 6 7
Function The high-order count value of watchdog timer is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note
Note: The following value is set by writing arbitrary data. * watchdog timer L `7F16' * watchdog timer H `FF16'
Figure 1.16.3 Watchdog Timer H (2) CPU Mode Register This register consists of the bits that select a stack page and an internal clock, as well as the bit that selects a count source of the watchdog timer. Figure 1.16.4 shows the CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
CPU mode register (CPUM) [Address 00FB16]
b 0 1 2 3 4 5 6 7
Name Fix these bits to `0' Stack page selection bit (Note) Watchdog timer L count source selection bit
Function
At reset 0 0
R O O O O
Undefined
W 0 0 O O x x O x
0 : Zero page 1 : 1 page 0 : f(XIN)/8 1 : f(XIN)/16
0 0
Undefined
Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (medium-speed mode)
Undefined
Undefined
0
Undefined
O
Undefined
Not implemented. Writing to this bit is disabled. This bit is undefined at reading.
Note: In the products whose RAM size is 192 bytes or less, set this bit to `0'.
Figure 1.16.4 CPU Mode Register
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1.16 Watchdog Timer
1.16.3 Operations of Watchdog Timer The operations of the watchdog timer are described below. Count Source The watchdog timer can select the following count sources using watchdog timer L count source selection bit of the CPU mode register: * f(XIN)/8 when the bit is `0' * f(XIN)/16 when the bit is `1' Internal Operation When the write instructions (Note 1) are executed to watchdog timer H, the following values are placed in watchdog timers H and L, regardless of the written value: * `FF16' into watchdog timer H * `7F16' into watchdog timer L The watchdog timer starts counting by writing to watchdog timer H, and every time the count source is input, the watchdog timer is decremented by 1. When bit 7 of watchdog timer H becomes `0' by a down count (Note 2), the internal reset signal changes from HIGH to LOW and the CPU enters the reset state. As a result, the internal state of the microcomputer is set as shown in Figure 1.17.2 Internal State at Reset in Section 1.17 Reset. Timer 1 goes to `FF16' to generate the wait time for the system releasing from reset, and then the watchdog timer starts counting, using f(XIN)/8 as the count source. When an underflow occurs in timer 1, the internal reset signal is raised to the HIGH state and the system is released from reset. The program is executed at the address stored in the reset vector area. Notes 1: Write instructions which generate write signals, such as STA, LDM, and CLB. 2: The time from writing data into watchdog timer H to placing `0' in bit 7 is 16384 (400016) cycles of the count source. Examples At f(XIN) = 8 MHz : * 16.384 ms; when the frequency of the count source is f(XIN)/8 * 32.768 ms; when the frequency of the count source is f(XIN)/16 Figure 1.16.5 shows the internal processing sequence during reset by the watchdog timer.
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1.16 Watchdog Timer
XIN pin Internal clock
2048 cycles of XIN pin input signal
Internal reset signal
Address bus Data bus SYNC pin
Bit 7 of Watchdog Timer H changes from `1' to `0'.
FFFE16 FFFF16 AL,AH AL AH
Internal Clock : Basic clock frequency of CPU, f(XIN)/2 (high-speed mode) after system is released from reset. AH, AL : Jump addresses stored in reset vector area. SYNC : CPU opcode fetch cycle (it cannot be examined externally because it is an internal signal). : Undefined
Figure 1.16.5 Internal Processing Sequence during Reset by Watchdog Timer Countermeasures with Watchdog Timer against Runaway Watchdog timer H is written to with the main routine, etc., to keep bit 7 from going to `0.' (keep it at `1'). In case of a program runaway by noise, watchdog timer H is not written to, so that bit 7 becomes `0' and the CPU returns to the reset state. Operations in Stop and Wait Modes * When the STP instruction is executed to enter the stop mode, the f(XIN) stops, causing the watchdog timer to stop counting. When the stop mode is terminated, the watchdog timer starts counting in response to the restarting of f(XIN) oscillation. * When the WIT instruction is executed to enter the wait mode, CPU stops operating, whereas the watchdog timer continues counting because the oscillation of f(XIN) does not stop. Note: The watchdog timer continues counting even during the oscillator start-up stabilization time (2048 cycles of the XIN pin input signal) after the stop mode is terminated, and the wait mode. Write to watchdog timer in order to prevent bit 7 of watchdog timer H from going to `0'. In the 7480 Group and 7481 Group, the valid/invalid of the STP and WIT instructions can be selected. Invalidating these instructions causes a runaway to be detected more effectively when the watchdog timer is used. For details on the setting of the valid/invalid of the stop and wait modes and the STP and WIT instructions, refer to Section 1.19 Power Saving Function.
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1.16 Watchdog Timer
1.16.4 Setting of Watchdog Timer Figure 1.16.6 shows the setting of the watchdog timer.
Procedure 1 Selecting watchdog timer L count source
b7 b0
00
CPU mode register (CPUM) [Address 00FB16]
Watchdog timer L count soure selection 0: f(XIN)/8 1: f(XIN)/16
Procedure 2 Writing to watchdog timer H (Note 1)
FF16 Watchdog timer H (WDTH) [Address 00EF16]
Arbitrary data (Note 2)
Notes 1: Writing to watchdog timer H starts counting. 2: The following values are set regardless of written data. * Watchdog Timer L `7F16' * Watchdog Timer H `FF16'
Note: Internal reset occurs if bit 7 of watchdog timer H becomes `0'. Therefore, write to watchdog timer H in the main routine in order to prevent bit 7 of watchdog timer H from going to `0'. Since the timer counts for the start-up stabilization time (2048 cycles of the XIN pin input signal), bit 7 of watchdog timer H must not be `0' during this period.
Figure 1.16.6 Setting of Watchdog Timer 1.16.5 Notes on Usage Pay attention to the following notes when the watchdog timer is used. Write to watchdog timer in the main routine in order to prevent bit 7 of watchdog timer H from going to `0'. The watchdog timer continues counting even during the oscillator start-up stabilization time (2048 cycles of the XIN pin input signal) after the stop mode is terminated, and the wait mode. Write to watchdog timer in order to prevent bit 7 of watchdog timer H from going to `0'. Do not operate the watchdog timer during system evaluation.
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1.17 Reset
1.17 Reset
When the LOW level is applied to the RESET pin for 2 s or more, the internal reset signal becomes LOW, and the CPU enters the reset state. Subsequently, when the HIGH level is applied to the RESET pin, the internal reset signal becomes HIGH, and the system is released from reset after the oscillator start-up stabilization time (Note) elapses. The program is resumed at the jump address stored in the reset vector area after the system is released from reset. In the 7480 Group and 7481 Group, even when bit 7 of watchdog timer H changes from `1' to `0', the internal reset signal changes from HIGH to LOW, causing the CPU to enter the reset state. For details of the watchdog timer, refer to Section 1.16 Watchdog Timer. Note: 2048 cycles of the XIN pin input signal (counted by timer 1). For an example of reset circuits, refer to Section 2.5 Reset.
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1.17 Reset
1.17.1 Reset Operations The reset operations are described below. When the power source voltage is within specifications (Note) and clock input oscillation frequency f(XIN) is stabled, the internal reset signal changes from HIGH to LOW by applying the LOW level to the RESET pin for 2 s or more, causing the CPU to enter the reset state. Then the HIGH level is applied to the RESET pin, so that the internal state of the microcomputer is set, as shown in Figure 1.17.2 Internal State at Reset. Timer 1 goes to `FF16' to generate the f(XIN) oscillator start-up stabilization time and then starts counting, using f(XIN)/8 as the count source. When an underflow occurs in timer 1, the internal reset signal becomes HIGH and the system is released from reset. The program is resumed at the address stored in the reset vector area. Note: * 2.7 V to 4.5 V at f(XIN) = (2.2 VCC-2) MHz * 4.5 V to 5.5 V at f(XIN) = 8 MHz Figure 1.17.1 shows the internal processing sequence after reset release.
VCC XIN pin Internal clock
2 s or more
RESET
2048 cycles of XIN pin input signal Internal reset Address bus Data bus SYNC pin Internal clock : Basic clock frequency of CPU = f(XIN)/2 AH, AL : Jump addresses stored in reset vector area SYNC : CPU opcode fetch cycle (it cannot be examined externally because it is an internal signal) : Undefined
FFFE16 FFFF16 AL,AH
AL
AH
Figure 1.17.1 Internal Processing Sequence after Reset Release
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1.17 Reset
1.17.2 Internal State at Reset Figure 1.17.2 shows the internal state at reset.
Address Contents of register
b7 b0
(1) (2) (3) (4) (5) (6) (7) (8) (9)
Port P0 direction register (P0D) Port P1 direction register (P1D) Port P4 direction register (P4D) Port P5 direction register (P5D) Port P0 pull-up control register (P0PCON) Port P1 pull-up control register (P1PCON) Port P4P5 input control register (P4P5CON) Edge polarity selection register (EG) A-D control register (ADCON)
00C116 00C316 00C916 00CB16 00D016 00D116 00D216 00D416 00D916 0
0016 0016 0000 0000 0016 00 0016 0000 01000
(10) STP instruction operation control register (STPCON) (11) Serial I/O status register (SIOSTS) (12) Serial I/O control register (SIOCON) (13) UART control register (UARTCON) (14) Bus collision detection control register (BUSARBCON) (15) Watchdog timer H (WDTH) (16) Timer X low-order (TXL) (17) Timer X high-order (TXH) (18) Timer Y low-order (TYL) (19) Timer Y high-order (TYH) (20) Timer 1 (T1) (21) Timer X mode register (TXM) (22) Timer Y mode register (TYM) (23) Timer XY control register (TXYCON) (24) Timer 1 mode register (T1M) (25) Timer 2 mode register (T2M) (26) CPU mode register (CPUM) (27) Interrupt request register 1 (IREQ1) (28) Interrupt request register 2 (IREQ2) (29) Interrupt control register 1 (ICON1) (30) Interrupt control register 2 (ICON2) (31) Program counter (PCH) (PCL) (32) Processor status register (PS) : Read back as undefined at reset.
00DE16 0 0 0 0 0 0 0 1 00E116 1 0 0 0 0 0 0 0 00E216 0016
00E316 1 1 1 1 0 0 0 0 00E516 00EF16 00F016 00F116 00F216 00F316 00F416 00F616 00F716 0016 FF16 FF16 FF16 FF16 FF16 FF16 0016 0016
00F816 0 0 0 0 0 0 1 1 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16 0 0016 0016 0000 0016 0000 0016 0000 Contents of FFFF16 Contents of FFFE16 1
Note: Since the contents of the registers and RAM not mentioned above are undefined at reset, initialize them by software. There are bits not implemented for some products. For these bits, refer to each register.
Figure 1.17.2 Internal State at Reset
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1.17 Reset
1.17.3 Notes on Usage Pay attention to the following notes when reset is used. Internal clock becomes f(XIN)/2 (high-speed mode) when the system is released from reset. Timer 1 and timer 2 are counting when the system is released from reset. Apply 0.32 V or less to the RESET pin at the time that power source voltage passes 2.7V, at power on. When the STP instruction is executed in normal operations, I/O port pins retain the states immediately before internal clock stops. If the CPU is then forced to the reset state from the stop mode, the I/O pins go to the input mode with the high-impedance state.
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1.18 Oscillation Circuit
1.18 Oscillation Circuit
The 7480 Group and 7481 Group are equipped with a built-in clock generator providing the clock necessary for operation of the microcomputer. An oscillation circuit is constructed by connecting a ceramic resonator between the XIN and XOUT pins (Note 1). Also, an external clock can be supplied to the clock generator (Note 2). The built-in feedback resistor connected between the XIN and XOUT pins allows the user to omit an external resistor. Notes 1: For an example of an oscillation circuit using a ceramic resonator, refer to Section 2.6 Oscillation Circuit. Consult the manufacturer of the resonator for the oscillator start-up stabilization time. 2: Also, for an external clock circuit, refer to Section 2.6 Oscillation Circuit. Use a 50% duty cycle pulse signal as the external clock input to the XIN pin. At this time, leave the XOUT pin open. 1.18.1 Block Diagram of Clock Generator The clock generator controls the oscillation circuit. The generated clock (internal clock ) is supplied to the CPU and the peripherals. Figure 1.18.1 shows the block diagram of the clock generator.
XIN
XOUT
1/2
1/4
Timer 1
Clock dividing ratio selection bit `0' 1/4 `1' Internal clock
Q
S R
S
Q
Q
S R
Reset STP instruction
STP instruction
WIT instruction
R
Reset Interrupt disable flag Interrupt request
Figure 1.18.1 Block Diagram of Clock Generator
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1.18 Oscillation Circuit
1.18.2 Register Associated with Oscillation Circuit Figure 1.18.2 shows the memory map of the register associated with the oscillation circuit.
00FB16
CPU mode register (CPUM)
Figure 1.18.2 Memory Map of Register Associated with Oscillation Circuit The CPU mode register consists of the bits that select a stack page and an internal clock, as well as the bit that selects a count source of the watchdog timer. Figure 1.18.3 shows the CPU mode register.
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
CPU mode register (CPUM) [Address 00FB16]
b 0 1 2 3 4 5 6 7
Name Fix these bits to `0'. Stack page selection bit (Note) Watchdog timer L count source selection bit
Function
At reset 0
R O O O O
Undefined
W 0 0 O O x x O x
0 : Zero page 1 : 1 page 0 : f(XIN)/8 1 : f(XIN)/16
0 0 0
Undefined
Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (medium-speed mode)
Undefined
Undefined
0
Undefined
O
Undefined
Not implemented. Writing to this bit is disabled. This bit is undefined at reading.
Note: In the products whose RAM size is 192 bytes or less, set this bit to `0'.
Figure 1.18.3 CPU Mode Register
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1.18 Oscillation Circuit
1.18.3 Oscillation Operations (1) Oscillation Operations The following clocks can be selected as internal clock by the clock division ratio selection bit of the CPU mode register. * XIN pin input divided by 2 (high-speed mode) when the bit is `0'. * XIN pin input divided by 8 (medium-speed mode) when the bit is `1'. Note: The oscillation circuit is held in the high-speed mode after the system is released from reset. (2) Oscillation in Stop Mode When the STP instruction is executed to enter the stop mode, internal clock stops in the HIGH state, and the oscillation of f(XIN) stops, as well. At this time, timer 1 goes to `FF16', and f(XIN)/8 is selected as the count source. CPU returns from stop mode by reset or accepting an external interrupt request (Note 1). In this time, internal clock is not supplied to the CPU until an underflow occurs in timer 1, though the oscillation of f(XIN) and internal clock are started. The reason is that oscillator start-up stabilization time is required when an external resonator is used. Note: Activate timer 1 and disable the acceptance of a timer 1 interrupt request before the STP instruction is executed. Notes 1: For interrupt sources that can be used to return from the stop mode, refer to Table 1.11.2 Interrupt Sources Available for CPU's Return from Stop/Wait Mode. For details of the stop mode, refer to Section 1.19.2 Stop Mode. (3) Oscillation in Wait Mode When the WIT instruction is executed to enter the wait mode, only internal clock stops in the HIGH state. When the CPU returns from the wait mode by reset or accepting an interrupt request (Note 2), the supply of internal clock to the CPU is resumed. Since f(XIN) continues oscillation during the wait mode, instructions can be executed immediately after the CPU returns from the wait mode. Notes 2: For interrupt sources that can be used to return from the wait mode, refer to Table 1.11.2 Interrupt Sources Available for CPU's Return from Stop/Wait Mode. For details of the wait mode, refer to Section 1.19.3 Wait Mode.
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1.18 Oscillation Circuit
1.18.4 Oscillator Start-Up Stabilization Time Oscillation is unstable immediately after oscillation is started in the oscillation circuit which uses a ceramic resonator. Necessary time for stabilizing oscillation is called an oscillator start-up stabilization time. The oscillator start-up stabilization time necessitated varies with the structure of the oscillation circuit used. Consult the manufacturer of the resonator for the oscillator start-up stabilization time. (1) Oscillator Start-Up Stabilization Time at Power On The oscillator start-up stabilizing time of 2048 cycles of the XIN pin input signal is automatically generated after the system is released from reset by timer 1 in the 7480 Group and 7481 Group (Note). Note: Timer 1 goes to `FF16' to select f(XIN)/8 as the count source. Figure 1.18.4 shows an oscillator start-up stabilization time at power on.
2.7 V (Note)
VCC
2 s or more
RESET pin
XIN
Oscillator start-up stabilization time 2048 cycles of XIN pin input signal
Internal reset
Internal reset released Note: At f(XIN) = (2.2 VCC-2) MHz. Apply 0.32 V or less to the RESET pin at the time that power source voltage passes 2.7 V.
Figure 1.18.4 Oscillator Start-Up Stabilization Time at Power On (2) Oscillator Start-Up Stabilization Time after Stop Mode Oscillation stops in the stop mode. When the CPU returns from the stop mode by reset or accepting an interrupt request, the oscillator start-up stabilization time of 2048 cycles of the input signal to the XIN pin is automatically generated by timer 1, as occurs at power on. 1.18.5 Notes on Usage Pay attention to the following notes when an oscillation circuit is used. The oscillation circuit is held in the high-speed mode after the system is released from reset. When a ceramic resonator is connected between the XIN and XOUT pins, consult the manufacturer of the resonator for the oscillator start-up stabilization time. When an external clock is input to the XIN pin, use a 50% duty cycle pulse signal as the external clock input to the XIN pin. At this time, leave the XOUT pin open. Activate timer 1 and disable the acceptance of a timer 1 interrupt request before the STP instruction is executed.
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1.19 Power Saving Function
1.19 Power Saving Function
The 7480 Group and 7481 Group are provided with the function to halt the CPU operation and make it stand by in the following two power saving modes by software: * Stop mode with the STP instruction * Wait mode with the WIT instruction Also, the valid/invalid of the STP and WIT instructions can be selected with the STP instruction operation control register. Table 1.19.1 lists the states of the microcomputer in the power saving modes. Figure 1.19.1 shows the transitions from the power saving modes. Table 1.19.1 States of Microcomputer in Power Saving Modes Stop Mode Clock f(XIN) Internal Clock CPU I/O Ports Event Count Mode Timers (external clock as count source) Other Modes (divided main clock as count source) Divided BRG output as synchronous clock External clock or its 1/16 as synchronous clock Stopped Stopped Retains the state at STP instruction execution Operating Operating Stopped Stopped Operating Operating Retains the state at STP instruction execution Registers associated with Timer 1 SFR Other registers Used to generate oscillator start-up stabilization time Retains the state at STP instruction execution Retains the state at STP instruction execution Retains the state at WIT instruction execution Retains the state at WIT instruction execution
Wait Mode Operating Stopped Retains the state at WIT instruction execution
Suspended at the HIGH level Suspended at the HIGH level
Serial I/O
RAM
Retains the state at WIT CPU Internal Registers instruction execution (Note) Note: The CPU internal registers are composed of the following six registers: * Accumulator * Index register X * Index register Y * Stack pointer * Program counter * Processor status register
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Stop mode
Interrupt request accepted Reset input
Wait mode
Interrupt request accepted
Reset input
Only RAM retained and other registers are in the reset state
Oscillator start-up stabilization time 2048 cycles of XIN pin input signal
RAM and the registers except timer 1 retained
Oscillator start-up stabilization time 2048 cycles of XIN pin input signal
RAM and the registers retained
No oscillator start-up stabilization time
System is released from reset Program executed at the address stored in reset vector areas
Interrupt service routine executed
The next address following STP or WIT instruction (program execution continued)
Figure 1.19.1 Transitions from Power Saving Modes
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1.19 Power Saving Function
1.19.1 Registers Associated with Power Saving Figure 1.19.2 shows the memory map of the registers associated with power saving.
00D416 Edge polarity selection register (EG)
00DE16 STP instruction operation control register (STPCON)
Figure 1.19.2 Memory Map of Registers Associated with Power Saving (1) STP Instruction Operation Control Register The STP instruction operation control register has only one bit that selects the valid/invalid of the STP and the WIT instruction. Figure 1.19.3 shows the STP instruction operation control register.
STP instruction operation control register
b7 b6 b5 b4 b3 b2 b1 b0
0000000
STP instruction operation control register (STPCON) [Address 00DE16]
b 0 1 2 3 4 5 6 7
Name STP and WIT valid/invalid selection bit (Note)
Function 0 : STP/WIT instruction valid 1 : STP/WIT instruction invalid
At reset 1 0 0 0 0 0 0 0
R O 0 0 0 0 0 0 0
W O x x x x x x x
Not implemented. Writing to these bits is disabled. These bits are `0' at reading.
Note: The STP and WIT instructions are invalid after the system is released from reset. When using these instructions, set STP and WIT valid/invalid selection bit of the STP instruction operation control register to `1', then set this bit to `0'. (Writing twice successively) When not using the STP and WIT instructions, set this bit to `1' either once or twice.
Figure 1.19.3 STP Instruction Operation Control Register
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(2) Edge Polarity Selection Register The edge polarity selection register consists of the bits that select the polarity of the valid edge of INT and CNTR pins, as well as the bit that selects the valid/invalid of key-on wakeup. Figure 1.19.4 shows the edge polarity selection register.
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0 Edge polarity selection register (EG) [Address 00D416]
b 0 1 2
Name INT0 edge selection bit INT1 edge selection bit CNTR0 edge selection bit 0 : Falling edge 1 : Rising edge
Function
At reset 0 0 0
R O O O
W O O O
3
CNTR1 edge selection bit
0 : Falling edge 1 : Rising edge 0: In event count mode, rising edge counted. : In pulse output mode, operation started at HIGH level output. : In pulse period measurement mode, a period from falling edge until falling edge measured. : In pulse width measurement mode, HIGH-level period measured. : In programmable one-shot output mode, one-shot HIGH pulse generated after operation started at LOW level output. : Interrupt request is generated by detecting falling edge. 1: In event count mode, falling edge counted. : In pulse output mode, operation started at LOW level output. : In pulse period measurement mode, a period from rising edge until rising edge measured. : In pulse width measurement mode, LOW-level period measured. : In programmable one-shot output mode, one-shot LOW pulse generated after operation started at HIGH level output. : Interrupt request is generated by detecting rising edge.
0
O
O
4 5
Not implemented. Writing to this bit is disabled. This bit is undefined at reading. 0 : P31/INT1 INT1 source selection bit at 1 : P00-P07 LOW level (for key-on wake-up) STP or WIT Not implemented. Writing to these bits are disabled. These bits are undefined at reading.
Undefined
Undefined
x
O
0
O
6 7
Undefined Undefined
Undefined Undefined
x x
Note: When setting bits 0 to 3, the interrupt request bit may be set to `1'. After setting the following, enable the interrupt. Disable interrupts Set the edge polarity selection register Set the interrupt request bit to `0'
Figure 1.19.4 Edge Polarity Selection Register
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1.19 Power Saving Function
1.19.2 Stop Mode (1) Operations in Stop Mode State in Stop Mode When the STP instruction is valid, its execution causes the CPU to enter the stop mode. In this mode, the CPU operation is halted because internal clock stops in the HIGH state. In addition, the operation of the peripherals stops as well, because the oscillation of f(XIN) stops. As a result, power dissipation can be reduced. Timer 1 goes to `FF16' to generate the oscillator start-up stabilization time necessary for terminating the stop mode, and a frequency of f(XIN)/8 is selected as the count source. Note: Timers continue counting in the event count mode, as done the serial I/O does when the external clock (or its 1/16) is selected as the synchronous clock. For the operations in the stop mode, refer to Table 1.19.1 States of Microcomputer in Power Saving Modes. The stop mode is terminated by reset or accepting an interrupt request, and the CPU returns to the normal mode. The operation at recovery from the stop mode by reset or accepting an interrupt request is described below. Recovery from Stop Mode by Reset Input By applying the LOW level to the RESET pin for 2 s or more in the stop mode, the CPU enters the reset state and is brought out of the stop mode, causing the XIN oscillation to resume. When the RESET pin is restored to the HIGH level, the oscillator start-up stabilization time is generated by timer 1. After the oscillator start-up stabilization time elapses, internal clock is supplied to the CPU. The program is executed at the address stored in the reset vector area. Figure 1.19.5 shows the operation at recovery from the stop mode by reset input.
Note: 2 cycles of internal clock STP instruction executed
Stop mode is terminated by reset input
Stop mode
VCC RESET
Undefined XIN pin : High-impedance state Oscillation start-up stabilization time 2048 cycles of XIN pin input signal 2 s or more STP instruction execution cycle (Note)
XIN pin
Internal reset
Figure 1.19.5 Operation at Recovery from Stop Mode by Reset Input For details of reset, refer to Section 1.17 Reset.
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1.19 Power Saving Function
Recovery from Stop Mode by Interrupt The stop mode is terminated and the XIN oscillation is resumed when an interrupt request is generated and its interrupt is acceptable in the stop mode. Next, the oscillator start-up stabilization time is generated by timer 1. After the oscillator start-up stabilization time elapses, internal clock is resumed and supplied to the CPU. The interrupt request used to terminate the stop mode is accepted and the interrupt service routine is executed. After the interrupt service routine is completed, the program is executed at the instruction following the STP instruction. Note: The state of timer 1 is affected by recovering from the stop mode. The interrupt sources used for recovery from the stop mode are as follows: * INT0, INT1 * CNTR0, CNTR1 * Serial I/O (only when external clock (or its 1/16) is selected as the synchronous clock) * Timer X and timer Y (only in event count mode) * Key inputs (in key-on wakeup) Figure 1.19.6 shows an operation example at recovery from the stop mode by the INT0 interrupt.
* INT0 interrupt is used for recovery from stop mode (rising edge detected)
STP instruction INT0 interrupt Stop mode is terminated executed request accepted by INT0 interupt STP instruction execution Oscillation start-up stabilization time cycle (Note 1) Stop mode 2048 cycles of XIN pin input signal
XIN
INT0 pin input FF16
RL
Undefined XIN pin : High-impedance state
RL
Counting down Contents of timer 1 0016 INT0 interrupt request bit Peripheral device
Operating Stop (Note 2) Operating
UF
CPU
Operating
Stop
Operating
RL : Reload UF : Underflow
Notes 1: 2 cycles of internal clock 2: Timer operates in event count mode. Serial I/O operates when the external clock input (or its 1/16) is used as the synchronous clock.
Figure 1.19.6 Operation Example at Recovery from Stop Mode by INT0 Interrupt
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1.19 Power Saving Function
(2) Transition to Stop Mode The transition from the normal mode to the stop mode is described below. Recovery from Stop Mode by Reset Input Execute the STP instruction while the STP instruction is valid. Recovery from Stop Mode by Accepting Interrupt Request Execute the STP instruction while the STP instruction is valid after the following sequence is completed: * Set the interrupt that is used to terminate the stop mode. * Clear the timer 1 interrupt enable bit to `0' (disabled). * Clear the timer 1 stop control bit to `0' (count operation). For the setting of the valid/invalid of the STP instruction, refer to Section 1.19.4 Setting of Valid/ Invalid of STP and WIT Instructions. 1.19.3 Wait Mode (1) Operations in Wait Mode State in Wait Mode When the WIT instruction is valid, its execution causes the CPU to enter the wait mode. In this mode, internal clock stops, though f(XIN) continues oscillation. As a result, the CPU is halted but the peripherals continue to operate. For the operations in the wait mode, refer to Table 1.19.1 States of Microcomputer at Power Saving Modes. The wait mode is terminated by reset or accepting an interrupt request, and the CPU returns to the normal mode. The operation at recovery from the wait mode by reset or accepting an interrupt request is described below. Recovery from Wait Mode by Reset Input By applying the LOW level to the RESET pin for 2 s or more in the wait mode, the CPU enters the reset state and is brought out of the wait mode. When the RESET pin is restored to the HIGH level, the oscillator start-up stabilization time is generated by timer 1. After the oscillator start-up stabilization time elapses, internal clock is supplied to the CPU. The program is executed at the address stored in the reset vector area. For details of reset, refer to Section 1.17 Reset. Recovery from Wait Mode by Interrupt The wait mode is terminated, when an interrupt request is generated and its interrupt is acceptable in the wait mode. Next, internal clock is resumed and supplied to the CPU. The interrupt request used to terminate the wait mode is accepted and the interrupt service routine is executed. After the interrupt service routine is completed, the program is executed at the instruction following the WIT instruction. All interrupt sources except the BRK instruction interrupt, are available for recovering from the wait mode.
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(2) Transition to Wait Mode The transition from the normal mode to the wait mode is described below. Recovery from Wait Mode by Reset Input Execute the WIT instruction while the WIT instruction is valid. Recovery from Wait Mode by Accepting Interrupt Request Execute the WIT instruction while the WIT instruction is valid after the interrupt for terminating the wait mode is set. For the setting of the valid/invalid of the WIT instruction, refer to Section 1.19.4 Setting of Valid/ Invalid of STP and WIT Instructions. 1.19.4 Setting of Valid/Invalid of STP and WIT Instructions In the 7480 Group and 7481 Group, the valid/invalid of the STP and WIT instructions can be selected with the STP instruction operation control register. The STP and the WIT instruction are invalid after the system is released from reset to prevent the program from a runaway. Writing twice successively to the STP instruction operation control register makes the STP and the WIT instruction valid, while non-successive writing to the register (for example, a single write) makes these instructions invalid. As the STP and the WIT instruction remain invalid after the system is released from reset, successive writing is used to prevent the clock oscillation from stopping due to erroneous data written during a program runaway. Figure 1.19.7 shows the setting of valid/invalid of the STP and WIT instructions.
Procedure 1 Setting interrupt disable flag of processor status register to `1' (interrupt disabled)
Procedure 2 Setting STP instruction operation control register (twice successive writing) (Note 1)
1. A write of `1'
b7 b0
1
STP instruction operation control register (STPCON) [Address 00DE16]
STP and WIT instructions invalid
2. Selection of valid/invalid of STP and WIT instructions (Note 2)
b7 b0
STP instruction operation control register (STPCON) [Address 00DE16]
STP and WIT valid/Invalid selection 0: Valid 1: Invalid
Notes 1: A single write to the STP instruction operation control register makes the STP and WIT instructions invalid. 2: If invalidating the STP and WIT instructions, the second write can be omitted.
Procedure 3 Clearing interrupt disable flag of processor status register to `0' (interrupt enabled) when using interrupts.
Figure 1.19.7 Setting of Valid/Invalid of STP and WIT Instructions
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1.19.5 Notes on Usage Pay attention to the following notes when the power saving function is used. (1) Setting of Valid/Invalid of STP and WIT Instructions To make the STP and the WIT instruction valid, write twice successively to the STP instruction operation control register while interrupts are disabled. REASON: Execution of an interrupt service routine may cause this register not to be successively written. (2) In Stop Mode After the CPU is brought out of the stop mode, timer 1 operates in the following conditions. Re-set timer 1 if necessary. * Contents of the timer 1 latch: `FF16' * Count source: f(XIN)/8 Since the A-D converter stops in the stop mode, execute the STP instruction after A-D conversion is completed. In the stop mode, timer X and timer Y continue counting only in the event count mode. Serial I/O operates only when an external clock (or its 1/16) is selected as the synchronous clock in the stop mode.
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1.20 Built-in PROM Version
1.20 Built-in PROM Version
A microcomputer with built-in PROM (PROM) is called a built-in programmable ROM version (built-in PROM version), in contrast to a mask ROM version. The 7480 Group and 7481 Group offer the following two versions of this type. * One Time PROM version The one time PROM are programmable only once. Erasing and reprogramming are not possible. * Built-in EPROM version (with a transparent window) The microcomputer has a built-in erasable PROM (EPROM) with a transparent window in top of the package. The built-in EPROM are programmable, erasable and reprogrammable. The built-in PROM version has the EPROM mode to program into the built-in PROM, in addition to the operation modes of the mask ROM version. For details, refer to Sections 1.3 Performance Overviews, 1.4 Pinouts, and 1.6 Functional Block Diagrams. The 7480 Group and 7481 Group support the built-in PROM version products listed in Table 1.20.1. Table 1.20.1 Supported Built-in PROM Version Products in 7480 Group and 7481 Group (As of September 1997) PROM RAM I/O Port Product Package Remarks (bytes) (bytes) M37480E8SP M37480E8FP M37480E8-XXXSP M37480E8-XXXFP M37480E8T-XXXSP M37480E8T-XXXFP M37481E8SP M37481E8FP M37481E8-XXXSP M37481E8-XXXFP M37481E8T-XXXSP M37481E8T-XXXFP M37481E8SS 16384 448 I/O ports: 18 Input ports: 8 32P4B One Time PROM Version 32P2W-A (shipped in blank) 32P4B One Time PROM Version (Including 4 analog 32P2W-A input pins.) 32P4B One Time PROM Version (Extended 32P2W-A operating temperature range version) 42P4B I/O ports: 24 Input ports: 12 One Time PROM Version 44P6N-A (shipped in blank) 42P4B One Time PROM Version 44P6N-A
(Including 8 analog 42P4B One Time PROM Version (Extended input pins.) 44P6N-A operating temperature range version) 42S1B-A Built-in EPROM Version
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1.20 Built-in PROM Version
1.20.1 EPROM Mode The built-in PROM version has the EPROM mode in addition to the operation modes of the mask ROM version. The EPROM mode is the mode used to program into and read from the built-in PROM. Programming, reading and erasing of the built-in PROM can be performed by the same operation as in the M5M27C256K. Table 1.20.2 lists the pin functions in the EPROM mode, and Figures 1.20.1 to 1.20.3 show the pinouts. Table 1.20.2 Pin Functions in EPROM Mode Built-in PROM version M5M27C256K VCC P33 VSS P11-P17, Pin name P20-P23, P30, P31, P40, P41 P00-P07 VREF P32 D0-D7
CE OE
VCC VPP VSS
A0-A14
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CE
VSS
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET VCC
D7 D6 D5 D4 D3 D2 D1 D0 A14 A13 VPP OE A12 A11
Outline 32P4B 32P2W-A (Note) : PROM pin (Same functions as M5M27C256K)
Note: The only differences between the 32P4B package product and the 32P2W-A package product are package shape and the absolute maximum ratings.
Figure 1.20.1 Pinout in EPROM Mode of 7480 Group
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VCC
VSS
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A10 A9 A8 A7 A6 A5 A4
A3 A2 A1 A0 CE
VSS
P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET P51 P50 VCC
D7 D6 D5 D4 D3 D2 D1 D0
Outline 42P4B (Note) 42S1B-A (M37481E8SS) : PROM pin (Same functions as M5M27C256K)
Note: The only differences between the 42P4B package product and the 44P6N-A package product are package shape, the absolute maximum ratings and the fact that the 44P6N-A package product has the AVSS pin.
Figure 1.20.2 Pinout in EPROM Mode of 7481 Group (1)
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A14 A13 VPP OE A12 A11
VSS VCC
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VPP
25
A13
A14
33
31
28
30
27
26
24
D4 D5 D6 D7 VSS A10 A9 A8 A7
P04 P05 P06 P07 P52 VSS P53 P17/SRDY P16/SCLK P15/TXD P14/RXD
32
29
23
P03 P02 P01 P00 P43 P42 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1
A12
D3
D2
D1
OE
D0
34 35 36 37 38 39 40 41 42 43 44
10 11 3 4 2 1 6 7 5 8 9
22 21 20 19
P30/INT0 RESET P51 P50 VCC VSS AVSS XOUT XIN VREF P20/IN0
A11
VSS VCC VSS
M37481E8-XXXFP M37481E8T-XXXFP
18 17 16 15 14 13 12
CE A0
A6
A5
A4
A3
A2
Outline 44P6N-A (Note) : PROM pin (Same functions as M5M27C256K)
Note: The only differences between the 42P4B package product and the 44P6N-A package product are package shape, the absolute maximum ratings and the fact that the 44P6N-A package product has the AVSS pin.
Figure 1.20.3 Pinout in EPROM Mode of 7481 Group (2)
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A1
P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1
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1.20 Built-in PROM Version
1.20.2 Pin Descriptions Tables 1.20.3 and 1.20.4 list pin descriptions in the Ordinary and EPROM modes. Table 1.20.3 Pin Descriptions (1) Pin VCC, VSS Mode Ordinary/ EPROM Name Power source Input/ Output Function * Apply the following voltage to the VCC pin: 2.7 V to 4.5 V (at f(XIN) = (2.2 VCC-2) MHz), or 4.5 V to 5.5 V (at f(XIN) = 8 MHz). * Apply 0 V to the VSS pin. Analog power source * Ground level input pin for the A-D converter * Apply the same voltage as for the VSS pin to the AVSS pin. Note: This pin is dedicated to the 44P6N-A package products in the 7481 Group. Input * Reference voltage input pin for A-D converter * Apply the following voltage to the VREF pin: 2 V to VCC when VCC = 2.7 V to 4.0 V, or 0.5 VCC to VCC when VCC = 4.0 V to 5.5 V. Note: When not using A-D converter, connect VREF pin to VCC. * CE input pin * Reset input pin * System Reset: Holding the LOW level for 2 s or more forces CPU into reset state. * Connect it to VSS pin. * I/O pins for clock generator * A ceramic resonator is connected between pins XIN and XOUT. * When an external clock is used, it is input to XIN pin, and leave XOUT pin open. * A feedback resistor is built in between pins XIN and XOUT.
AVSS
Ordinary/ EPROM
VREF
Ordinary
Reference voltage input
EPROM
RESET
Mode input Reset input
Input Input
Ordinary
EPROM XIN Ordinary/ EPROM XOUT Ordinary/ EPROM
Reset input Clock input
Input Input
Clock output
Output
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1.20 Built-in PROM Version
Table 1.20.4 Pin Descriptions (2) Pin Mode Name I/O port P0 Input/ Output I/O * 8-bit I/O port pins * The output structure is CMOS output. * When an input port is selected, a pull-up transistor can be connectable by the bit. * In input mode, a key-on wake up function is provided. EPROM P10-P17 Ordinary Data I/O D0-D7 I/O port P1 I/O I/O * Data (D0-D7) I/O pins * 8-bit I/O port pins * The output structure is CMOS output. * When an input port is selected, a pull-up transistor can be connected by the 4 bits. * P12 and P13 serve the alternative functions of the timer output pins T0 and T1. * P14, P15, P16, and P17 serve the alternative functions of the serial I/O pins RxD, TxD, SCLK and SRDY, respectively. EPROM P20-P27 Ordinary Address input A4-A10 Input port P2 Input Input * P11-P17 are the address (A4-A10) input pins. * Leave P10 open. * 8-bit input port pins * P20-P27 serve the alternative functions of the analog input pins IN0-IN7. Note: The 7480 Group has only four pins of P20-P23 (IN0-IN3). * P20-P23 are the address (A0-A3) input pins. * Leave P24-P27 open. Input * 4-bit input port pins * P30 and P31 serve the alternative functions of the external interrupt input pins INT0 and INT1. EPROM Address input A11, A12 Mode input VPP input P40-P43 Ordinary I/O port P4 I/O Input * P30, P31 are the address (A11, A12) input pins. * P32 pin is the OE input pin. * P33 pin is the VPP input pin used to apply VPP when programming and program verifying. * 4-bit I/O port pins * The output structure is N-channel open-drain outputs with built-in clamping diodes. * P40 and P41 serve the alternative functions of the timer I/O pins CNTR0 and CNTR1. Note: The 7480 Group has only two pins of P40 and P41. EPROM P50-P53 Ordinary Address input A13, A14 I/O port P5 I/O Input * P40, P41 are the address (A13, A14) input pins. * Leave P42, P43 open. * 4-bit I/O port pins * The output structure is N-channel open-drain outputs with built-in clamping diodes. Note: The 7480 Group is not provided with port P5. * Leave port P5 open. Function
P00-P07 Ordinary
EPROM P30-P33 Ordinary
Address input A0-A3 Input port P3
Input
EPROM
Input port P5
Input
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1.20 Built-in PROM Version
1.20.3 Reading, Programming and Erasing of Built-in PROM The built-in PROM version can be used in the EPROM mode by setting the RESET pin to LOW. Reading, programming, and erasing of the built-in PROM in the EPROM mode are described below. Also, Table 1.20.5 lists the I/O signals in the EPROM mode. (1) Reading from Built-in PROM * 0 V is applied to the RESET pin, and 5 V to the VCC pin. * Address signals (A0-A14) are input, and the OE and the CE pins are set to LOW. Then, the contents of PROM are placed on data I/O pins (D0-D7). * The CE or the OE pins are set to HIGH. Then, data I/O pins (D0-D7) float. (2) Programming into Built-in PROM * 0 V is applied to the RESET pin, and 5 V to the VCC pin. * The OE pin is set to HIGH and VPP is applied to the VPP pin. Then, the CPU enters the program mode. * Addresses are set to address input pins (A0-A14), and the 8-bit data to be programmed is placed in parallel, on data I/O pins (D0-D7). * Setting the CE pin to LOW starts programming. Specify addresses 400016 through 7FFF16 when programming with the PROM programmer. Also, set all addresses 000016 through 3FFF16 to `FF16' when programming into addresses 000016 through 7FFF16. (3) Erasing * Only the built-in EPROM version with a window (M37481E8SS) is erasable. * The EPROM can be erased when exposed to ultraviolet light with a wavelength of 2537 A. * Integrated dose necessary for erasure is a minimum of 15 W*s/cm 2. Table 1.20.5 I/O Signals in EPROM Mode Pin name Mode Read Output disable Write Write-verify Write disable
CE OE
VPP VCC VCC VPP VPP VPP
VCC
RESET
D0-D7 Output Floating
VIL VIL VIL VIH VIH
VIL VIH VIH VIL VIH
VCC
0V
Input Output Floating
Note: VIL represents the LOW input voltage, and VIH, the HIGH input voltage.
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1.20 Built-in PROM Version
1.20.4 Notes on Usage Pay attention to the following notes when the built-in PROM version is used. (1) All Products of Built-in PROM Version Products Programming into Built-in PROM * A high voltage is used to program into the PROM. Be careful not to apply an overvoltage to pins, especially when power is turned on. * The use of a dedicated programming adapter (Note) is recommended when the PROM programming is performed, so that general-purpose PROM programmers are available for programming. Reading from Built-in PROM The use of a dedicated programming adapter (Note) is recommended when the PROM contents are read, so that general-purpose PROM programmers are available for reading. Note: Refer to Data Book DEVELOPMENT SUPPORT TOOLS FOR MICROCOMPUTERS for the dedicated programming adapter. (2) One Time PROM Version The one time PROM version (a blank product) is neither tested nor screened since Mitsubishi's assembly process. To improve reliability after programming, it is suggested that these products are used only after programming and verification, according to the procedure shown in Figure 1.20.4, is completed.
Programming with PROM Programmer
Screening (at 150C for 40 hours)
(Note 1) Notes 1: Exposure to a high temperature of be within 100 hours. The M37480E8SP/FP, M37481E8SP/FP and M37481E8SS are not available for automotive controls because they are not extended operating temperature versions, which are used in automotive controls. The M37481E8SS is for the program-evaluation only. It cannot be as the final product as well as in automotive controls. 2: Implementation evaluation will reject those damaged by surge during handling. (Note 2)
Verifying with PROM Programmer
Function check in target device
Figure 1.20.4 Programming and Verification of One Time PROM Version
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1.20 Built-in PROM Version
(3) Built-in EPROM Version The built-in EPROM version can be used for program development only. Use them only for program development and implementation evaluation. Sunlight and fluorescent light include light that may erase the information programmed in the builtin PROM. When using the EPROM version in the read mode, be sure to cover the transparent glass portion with a seal. This seal to cover the transparent glass portion is prepared by Mitsubishi. Be careful not to bring the seal into contact with the microcomputer lead wires when covering the portion with the seal because this seal is made of metal (aluminum). Before erasing data, clean the transparent glass. If any finger stain or seal adhesive is stuck to the transparent glass, this prevents ultraviolet rays from passing, thereby affecting the erase characteristic adversely.
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1.21 Electrical Characteristics
1.21 Electrical Characteristics
1.21.1 Electrical Characteristics (1) Electrical Characteristics of 7480 Group For the 7480 Group, Table 1.21.1 lists the absolute maximum ratings, and Tables 1.21.2 and 1.21.3 list the recommended operating conditions. Also, Tables 1.21.4 and 1.21.5 list the electrical characteristics, and Table 1.21.6 lists the A-D conversion characteristics. Table 1.21.1 Absolute Maximum Ratings of 7480 Group Symbol VCC VI VO Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature range Storage temperature range Ratings Conditions All voltages are measured based on -0.3 to 7 VSS. -0.3 to VCC+0.3 Output transistors are in the cut-off state. -0.3 to VCC+0.3 Ta = 25C 1000 (Note 1) -20 to 85 (Note 2) -40 to 150 (Note 3) Unit V V V mW C C
Notes 1: 500 mW for 32P2W-A package. 2: -40 C to 85 C for extended operating temperature range version. 3: -65 C to 150 C for extended operating temperature range version. Table 1.21.2 Recommended Operating Conditions of 7480 Group (1) (Note 1) Symbol VCC VSS VIH VIH VIH VIH VIL VIL VIL VIL VIL II Power source voltage Power source voltage HIGH input voltage P00-P07, P10-P17 HIGH input voltage P20-P23 HIGH input voltage VCC = 4.5 V to 5.5V P30-P33, P40, P41 (Note 2) VCC = 2.7 V to 4.5V HIGH input voltage XIN, RESET LOW input voltage P00-P07, P10-P17 LOW input voltage P20-P23 LOW input voltage P30-P33, P40, P41 LOW input voltage XIN LOW input voltage RESET Input current P40, P41 (Note 2) VI > VCC VCC = 4.5 V to 5.5V VCC = 2.7 V to 4.5V 0.8VCC 0.7VCC 0.8VCC 0.9VCC 0.8VCC 0 0 0 0 0 0 Parameter f(XIN) = 8 MHZ f(XIN) = (2.2VCC-2.0) MHz Limits Min. 4.5 2.7 Typ. 5 3 0 VCC VCC VCC VCC VCC 0.2VCC 0.25VCC 0.4VCC 0.3VCC 0.16VCC 0.12VCC 1 Max. 5.5 4.5 Unit V V V V V V V V V V V V V V mA
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85 C (Ta = -40 C to 85 C for extended operating temperature range version), unless otherwise noted. For the clamping diodes of port P4, refer to (4) Level Shift Ports in Section 1.10.3 I/O Ports. 2: When voltage is applied through a resistor, current I of 1 mA or less maintains VI > VCC. For this circuit, refer to Figure 1.10.11 Port P4 and P5 Circuit.
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1.21 Electrical Characteristics
Table 1.21.3 Recommended Operating Conditions of 7480 Group (2) (Note 1) Symbol Parameter Min. Limits Typ. Max. -30 -30 60 60 -10 20 -5 10 f(XIN) = 8 MHz f(XIN) = 4 MHz 2 1 500 250 2 1 Unit mA mA mA mA mA mA mA mA MHz MHz kHz kHz MHz MHz
IOH(sum) HIGH output sum current P00-P07 IOH(sum) HIGH output sum current P10-P17 IOL(sum) LOW output sum current P00-P07, P40, P41 IOL(sum) LOW output sum current P10-P17 IOH(peak) HIGH output peak current P00-P07, P10-P17 IOL(peak) LOW output peak current P00-P07, P10-P17, P40, P41 IOH(avg) HIGH output average current P00-P07, P10-P17 (Note 2) IOL(avg) f(CNTR) LOW output average current P00-P07, P10-P17, P40, P41 (Note 2) Timer input frequency CNTR0 (P40) CNTR1 (P41) (Note 3)
Serial I/O when selecting clock f(XIN) = 8 MHz clock input frequency synchronous serial I/O f(XIN) = 4 MHz f(SCLK) SCLK (P16) w h e n s e l e c t i n g f(XIN) = 8 MHz f(XIN) = 4 MHz (Note 3) UART f(XIN) Clock input oscillation VCC = 4.5V to 5.5V
8 MHz 2.2VCC-2.0 MHz frequency (Note 3) VCC = 2.7V to 4.5V Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85 C (Ta = -40 C to 85 C for extended operating temperature range version), unless otherwise noted. For the clamping diodes of port P4, refer to (4) Level Shift Ports in Section 1.10.3 I/O Ports. 2: Output average currents IOH(avg) and IOL(avg) are average values for a period of 100 ms. 3: The frequency is the value at a 50% duty cycle. 4: Connect a bypass capacitor of capacity 0.1 F between VCC and VSS, and one of capacity 0.01F between VREF and VSS.
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Table 1.21.4 Electrical Characteristics of 7480 Group (1) (Note 1) Symbol VOH VOL Parameter HIGH output voltage P00-P07, P10-P17 LOW output voltage Test conditions VCC = 5 V, IOH = -5 mA VCC = 3 V, IOH = -1.5 mA VCC = 5 V, IOL = 10 mA Min. 3 2 2 1 0.5 0.3 0.5 0.3 VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V 0.5 0.3 5 3 5 3 VCC = 5 V 5 3 5 3 -5 -3 -0.25 -0.08 -0.5 -0.18 -1.0 -0.35 -5 -3 -5 -3 -5 -3 Limits Typ. Max. Unit V V V V V V V V V V
P00-P07, P10-P17, P40, P41 VCC = 3 V, IOL = 3 mA Hysteresis P00-P07 (Note 2), VCC = 5 V VT+-VT- P30-P33, P40, P41 VCC = 3 V VT+-VT- Hysteresis RESET VT+-VT- IIH IIH IIH IIH Hysteresis P14/RxD, P16/SCLK HIGH input current P00-P07, P10-P17 HIGH input current P30-P33, P40, P41 HIGH input current P20-P23 HIGH input current XIN, RESET LOW input current P00-P07, P10-P17 LOW input current P30-P33, P40, P41 LOW input current P20-P23 LOW input current XIN, RESET VCC = 5 V VCC = 3 V when used as RxD, SCLK VI = VCC, No pull-up transistor VI = VCC = 5 V VI = VCC = 3 V VI = VCC, when not
selecting analog input VCC = 3 V VCC = 5 V VI = VCC, when XIN is stopped VI = 0 V, No pull-up transistor VI = 0 V (Note 3), VCC = 3 V VCC = 5 V VCC = 3 V VCC = 5 V
IIL
IIL IIL IIL
Pull-up transistor used VCC = 3 V VCC = 5 V VI = 0 V VCC = 3 V VCC = 5 V VI = 0 V, when not selecting analog input VCC = 3 V VCC = 5 V VI = 0 V, when XIN is stopped VCC = 3 V
A A A A A A A A A A mA mA A A A A A A
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85C (Ta = -40 C to 85C for extended operating temperature range version), unless otherwise noted. 2: The limits when the key-on wakeup function of port P0 is used 3: When represented with electric resistance, the corresponding values are as follows: * VCC = 5 V: 5 k (Min.), 10 k (Typ.), and 20 k (Max.) * VCC = 3 V: 8.6 k (Min.), 16.7 k (Typ.), and 37.5 k (Max.)
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Table 1.21.5 Electrical Characteristics of 7480 Group (2) (Note) Symbol Parameter Test conditions High-speed mode, f(XIN) = 4 MHz, VCC = 5 V High-speed mode, f(XIN) = 4 MHz, VCC = 3 V High-speed mode, f(XIN) = 8 MHz, VCC = 5 V Medium-speed mode, f(XIN) = 4 MHz, VCC = 5 V Medium-speed mode, f(XIN) = 4 MHz, VCC = 3 V Medium-speed mode, f(XIN) = 8 MHz, VCC = 5 V High-speed mode, f(XIN) = 4 MHz High-speed mode, f(XIN) = 8 MHz Medium-speed mode, f(XIN) = 4 MHz Medium-speed mode, f(XIN) = 8 MHz f(XIN) = 0 MHz, VCC = 5 V At wait No A-D conversion During A-D conversion No A-D conversion During A-D conversion No A-D conversion During A-D conversion No A-D conversion During A-D conversion No A-D conversion During A-D conversion No A-D conversion During A-D conversion VCC = 5 V VCC = 3 V VCC = 5 V VCC = 5 V VCC = 3 V VCC = 5 V Ta = 25 C Ta = 85 C 2.0 Min. Limits Typ. 3.5 4 1.8 2 7 7.5 1.75 2 0.9 1 3.5 3.75 1 0.5 2 0.9 0.45 1.8 0.1 1 Max. 7 8 3.6 4 14 15 3.5 4 1.8 2 7 7.5 2 1 4 1.8 0.9 3.6 1 10 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
ICC
Power source current
At system operating
At stop
A A
V
VRAM
RAM back-up voltage
At clock stop
Note: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85C (Ta = -40 C to 85C for extended operating temperature range version), unless otherwise noted.
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Table 1.21.6 A-D Conversion Characteristics of 7480 Group (Note) Symbol - - TCONV VVREF Parameter Resolution Absolute accuracy VCC (except quantification error) VCC Conversion time VCC VCC Reference voltage VCC = VREF = 5.0 V = = = = 2.7V to 4.5V, f(XIN) = 4MHZ 4.5V to 5.5V, f(XIN) = 8MHZ 2.7 V to 4.0V 2 4.0 V to 5.5 V 0.5 VCC 12 35 Test conditions Min. Limits Typ. Max. 8 2 25 12.5 VCC VCC 100 VREF Unit bits LSB
RLADDER Ladder resistor 0 VIA Analog input voltage VREF = 5.0 V 50 143 IVREF Reference power input current Note: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85C (Ta = -40 C to 85C operating temperature range version), unless otherwise noted.
416 for extended
s s V V k V A
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(2) Electrical Characteristics of 7481 Group For the 7481 Group, Table 1.21.7 lists the absolute maximum ratings, and Tables 1.21.8 and 1.21.9 list the recommended operating conditions. Also, Tables 1.21.10 and 1.21.11 list the electrical characteristics, and Table 1.21.12 lists the A-D conversion characteristics. Table 1.21.7 Absolute Maximum Ratings of 7481 Group Symbol VCC VI VO Pd Topr Tstg Parameter Power source voltage Input voltage Output voltage Power dissipation Operating temperature range Storage temperature range Ratings Conditions All voltages are measured based on -0.3 to 7 VSS. -0.3 to VCC+0.3 Output transistors are in the cut-off state. -0.3 to VCC+0.3 Ta = 25C 1000 (Note 1) -20 to 85 (Note 2) -40 to 150 (Note 3) Unit V V V mW C C
Notes 1: 500 mW for 44P6N-A package. 2: -40 C to 85 C for extended operating temperature range version. 3: -65 C to 150 C for extended operating temperature range version. Table 1.21.8 Recommended Operating Conditions of 7481 Group (1) (Note 1) Symbol VCC VSS VIH VIH VIH VIH VIL VIL VIL VIL VIL II Power source voltage Power source voltage HIGH input voltage P00-P07, P10-P17 VCC = 4.5 V to 5.5V P30-P33, P40-P43, P50-P53 (Note 2) VCC = 2.7 V to 4.5V HIGH input voltage XIN, RESET LOW input voltage P00-P07, P10-P17 LOW input voltage P20-P27 LOW input voltage VCC = 4.5 V to 5.5V P30-P33, P40-P43, P50-P53 (Note 2) VCC = 2.7 V to 4.5V LOW input voltage XIN LOW input voltage RESET Input current P40-P43, P50-P53 (Note 2) VI > VCC HIGH input voltage P20-P27 HIGH input voltage 0.8VCC 0.7VCC 0.8VCC 0.9VCC 0.8VCC 0 0 0 0 0 0 Parameter f(XIN) = 8 MHZ f(XIN) = (2.2VCC-2.0) MHz Limits Min. 4.5 2.7 Typ. 5 3 0 VCC VCC VCC VCC VCC 0.2VCC 0.25VCC 0.4VCC 0.3VCC 0.16VCC 0.12VCC 1 Max. 5.5 4.5 Unit V V V V V V V V V V V V V V mA
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85 C (Ta = -40 C to 85 C for extended operating temperature range version), unless otherwise noted. For the clamping diodes of port P4, refer to (4) Level Shift Ports in Section 1.10.3 I/O Ports. 2: When voltage is applied through a resistor, current I of 1 mA or less maintains VI > VCC. For this circuit, refer to Figure 1.10.11 Port P4/P5 Circuitry.
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Table 1.21.9 Recommended Operating Conditions of 7481 Group (2) (Note 1) Symbol Parameter Min. Limits Typ. Max. -30 -30 60 60 -10 20 -5 10 2 1 500 250 2 1 Unit mA mA mA mA mA mA mA mA MHz MHz kHz kHz MHz MHz MHz
IOH(sum) HIGH output sum current P00-P07 IOH(sum) HIGH output sum current P10-P17 IOL(sum) LOW output sum current P00-P07, P40-P43, P50-P52 IOL(sum) LOW output sum current P10-P17, P53 IOH(peak) HIGH output peak current P00-P07, P10-P17 IOL(peak) LOW output peak current P00-P07, P10-P17, P40-P43, P50-P53 IOH(avg) HIGH output average current P00-P07, P10-P17 (Note 2) IOL(avg) f(CNTR) LOW output average current P00-P07, P10-P17, P40-P43, P50-P53 (Note 2) f(XIN) = 8 MHz Timer input frequency CNTR0 (P40) CNTR1 (P41) (Note 3) f(XIN) = 4 MHz MHz MHz MHz MHz
Serial I/O when selecting clock f(XIN) = 8 clock input frequency synchronous serial I/O f(XIN) = 4 f(SCLK) SCLK (P16) w h e n s e l e c t i n g f(XIN) = 8 f(XIN) = 4 (Note 3) UART f(XIN) Clock input oscillation VCC = 4.5V to 5.5V
8 2.2VCC-2.0 MHz frequency (Note 3) VCC = 2.7V to 4.5V Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85 C (Ta = -40 C to 85 C for extended operating temperature range version), unless otherwise noted. For the clamping diodes of port P4, refer to (4) Level Shift Ports in Section 1.10.3 I/O Ports. 2: Output average currents IOH(avg) and IOL(avg) are average values for a period of 100 ms. 3: The frequency is the value at a 50% duty cycle. 4: Connect a bypass capacitor of capacity 0.1 F between VCC and VSS, and one of capacity 0.01F between VREF and VSS.
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Table 1.21.10 Electrical Characteristics of 7481 Group (1) (Note 1) Symbol VOH Parameter HIGH output voltage Test conditions VCC = 5 V, IOH = -5 mA V, IOH = -1.5 mA V, IOL = 10 mA V, IOL = 3 mA V V 0.5 0.3 0.5 VCC = 5 V VCC = 3 V VCC = 5 V VCC = 3 V 0.3 0.5 0.3 5 3 5 3 5 3 5 3 -5 -3 -0.25 -0.08 -0.5 -0.18 -1.0 -0.35 -5 -3 -5 -3 -5 -3 Min. 3 2 2 1 Limits Typ. Max. Unit V V V V V V V V V V
P00-P07, P10-P17 VCC = 3 LOW output voltage P00-P07, VCC = 5 VOL P10-P17, P40-P43, P50-P53 VCC = 3 Hysteresis P00-P07 (Note 2), VCC = 5 VT+-VT- P30-P33, P40-P43, P50-P53 VCC = 3 VT+-VT- Hysteresis RESET VT+-VT- IIH IIH IIH IIH Hysteresis P14/RxD, P16/SCLK HIGH input current P00-P07, P10-P17 HIGH input current
VCC = 5 V VCC = 3 V when used as RxD, SCLK VI = VCC, No pull-up transistor
VI = VCC = 5 V P30-P33, P40-P43, P50-P53 VI = VCC = 3 V HIGH input current VCC = 5 V VI = VCC, when not P20-P27 selecting analog input VCC = 3 V VCC = 5 V HIGH input current VI = VCC, when XIN XIN, RESET LOW input current P00-P07, P10-P17 is stopped VI = 0 V, No pull-up transistor VI = 0 V (Note 3), VCC = 3 V VCC = 5 V VCC = 3 V
IIL
IIL IIL IIL
VCC = 5 V Pull-up transistor used VCC = 3 V VCC = 5 V LOW input current VI = 0 V VCC = 3 V P30-P33, P40-P43, P50-P53 VCC = 5 V LOW input current VI = 0 V, when not P20-P27 selecting analog input VCC = 3 V LOW input current XIN, RESET VI = 0 V, when XIN is stopped VCC = 5 V VCC = 3 V
A A A A A A A A A A mA mA A A A A A A
Notes 1: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85C (Ta = -40 C to 85C for extended operating temperature range version), unless otherwise noted. 2: The limits when the key-on wakeup function of port P0 is used 3: When represented with electric resistance, the corresponding values are as follows: * VCC = 5 V: 5 k (Min.), 10 k (Typ.), and 20 k (Max.) * VCC = 3 V: 8.6 k (Min.), 16.7 k (Typ.), and 37.5 k (Max.)
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Table 1.21.11 Electrical Characteristics of 7481 Group (2) (Note) Symbol Parameter Test conditions High-speed mode f(XIN) = 4 MHz VCC = 5 V High-speed mode f(XIN) = 4 MHz VCC = 3 V High-speed mode f(XIN) = 8 MHz VCC = 5 V Medium-speed mode f(XIN) = 4 MHz VCC = 5 V Medium-speed mode f(XIN) = 4 MHz VCC = 3 V Medium-speed mode f(XIN) = 8 MHz VCC = 5 V High-speed mode f(XIN) = 4 MHz High-speed mode f(XIN) = 8 MHz Medium-speed mode f(XIN) = 4 MHz Medium-speed mode f(XIN) = 8 MHz f(XIN) = 0 MHz VCC = 5 V At wait No A-D conversion During A-D conversion No A-D conversion During A-D conversion No A-D conversion During A-D conversion No A-D conversion During A-D conversion No A-D conversion During A-D conversion No A-D conversion During A-D conversion VCC = 5 V VCC = 3 V VCC = 5 V VCC = 5 V VCC = 3 V VCC = 5 V Ta = 25 C Ta = 85 C 2.0 Min. Limits Typ. 3.5 4 1.8 2 7 7.5 1.75 2 0.9 1 3.5 3.75 1 0.5 2 0.9 0.45 1.8 0.1 1 Max. 7 8 3.6 4 14 15 3.5 4 1.8 2 7 7.5 2 1 4 1.8 0.9 3.6 1 10 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA
ICC
Power source current
At system operating
At stop
A A
V
VRAM
RAM back-up voltage
At clock stop
Note: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85C (Ta = -40 C to 85C for extended operating temperature range version), unless otherwise noted.
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Table 1.21.12 A-D Conversion Characteristics of 7481 Group (Note) Symbol - - TCONV VVREF Parameter Resolution Absolute accuracy (except quantification error) Conversion time Reference voltage VCC = VREF = 5.0 V VCC VCC VCC VCC = = = = 2.7V to 4.5V, f(XIN) = 4MHZ 4.5V to 5.5V, f(XIN) = 8MHZ 2.7 V to 4.0V 2 4.0 V to 5.5 V 0.5 VCC Test conditions Min. Limits Typ. Max. 8 2 25 12.5 VCC VCC 100 VREF Unit bits LSB
35 RLADDER Ladder resistor 12 0 VIA Analog input voltage 143 50 IVREF Reference power input current VREF = 5.0 V Note: VCC = 2.7 V to 5.5 V, VSS = 0 V, and Ta = -20 C to 85C (Ta = -40 C to 85C temperature range version), unless otherwise noted.
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1.21.2 Necessary Conditions for Timing and Switching Characteristics Table 1.21.13 lists the necessary conditions for timing and the switching characteristics of the 7480 Group and 7481 Group, and Figure 1.21.1 shows the timing diagram. Table 1.21.13 Necessary Conditions for Timing and Switching Characteristics (Note) Symbol Clock synchronous tC(SCLK) tWH(SCLK) tWL(SCLK) tSU(RxD-SCLK) th(SCLK-RxD) td(SCLK-TxD) tC(SCLK) tWH(SCLK) tWL(SCLK) Parameter Serial I/O clock input cycle time Serial I/O clock input HIGH pulse width Serial I/O clock input LOW pulse width Serial I/O input set-up time Serial I/O input hold time Serial I/O output delay time Serial I/O clock input cycle time Serial I/O clock input HIGH pulse width Serial I/O clock input LOW pulse width 500 220 220 Min. 2000 880 880 160 80 100 Limits Typ. Max. Unit ns ns ns ns ns ns ns ns ns
Note: Values at VCC = 4.5 V to 5.5 V, VSS = 0 V, Ta = -40 C to 85C, and f(XIN) = 8 MHz
UART
tc(SCLK) tWL(SCLK)
0.8VCC 0.8VCC 0.2VCC 0.2VCC
tWH(SCLK)
0.8VCC
SCLK
tsu(RXD-SCLK)
0.8VCC
th(SCLK-RXD)
0.8VCC 0.2VCC
RXD
td(SCLK-TXD)
0.2VCC
TXD
Figure 1.21.1 Timing Diagram 1.21.3 Typical Characteristics of Power Source Current The typical characteristics of the power source current described in this section are based on a limited number of samples in the 7480 Group and 7481 Group. `Typical values' are not guaranteed. For the limits, refer to section 1.21.1 Electrical Characteristics. Figure 1.21.2 shows a measurement circuit of typical power source current characteristics.
7480 Group 7481 Group
ICC VCC
A
0 to 5.5V
VSS XIN XOUT
Figure 1.21.2 Measurement Circuit of Typical Power Source Current Characteristics 1-190
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(1) VCC-ICC Characteristics Figures 1.21.3 to 1.21.6 show the VCC-ICC characteristics of the 7480 Group and 7481 Group.
Conditions: System operates at 25C, f(XIN) = 8 MHz (with a ceramic resonator) in High-speed mode 10.0
9.0 During A-D conversion 8.0
Power source current ICC [mA]
7.0
6.0 No A-D conversion 5.0
4.0
3.0
2.0
1.0
0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage VCC [V]
Figure 1.21.3 VCC-ICC Characteristics (at System Operating in High-Speed Mode)
5.0
Conditions: System operates at 25C, f(XIN) = 8 MHz (with a ceramic resonator) in Medium-speed mode
Power source current ICC [mA]
4.0 During A-D conversion 3.0 No A-D conversion
2.0
1.0
0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage VCC [V]
Figure 1.21.4 VCC-ICC Characteristics (at System Operating in Medium-Speed Mode)
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0.3
Conditions: 25C, f(XIN) = 8 MHz (with a ceramic resonator) in wait mode
Power source current ICC [mA]
High-speed mode 0.2
Medium-speed mode 0.1
0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage VCC [V]
Figure 1.21.5 VCC-ICC Characteristics (in Wait Mode)
0.8
Conditions: 25C, f(XIN) = 0 MHz in stop mode
0.7
0.6
Power source current ICC [nA]
0.5
0.4
0.3
0.2
0.1
0.0 2.0 3. 0 4. 0 5.0 6. 0 7. 0
Power source voltage VCC [V]
Figure 1.21.6 VCC-ICC Characteristic (in Stop Mode)
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(2) f(XIN)-ICC Characteristics Figures 1.21.7 and 1.21.8 show the f(XIN)-ICC characteristics of the 7480 Group and 7481 Group.
Conditions: System operates at 25 C, with a ceramic resonator in High-speed mode 6.0
Power source current ICC [mA]
5.0
4.0
3.0
2.0 : VCC = 5 V (During A-D conversion) : VCC = 5 V (No A-D conversion) : VCC = 3 V (During A-D conversion) : VCC = 3 V (No A-D conversion) 0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
1.0
0.0
Clock input oscillation frequency f(XIN) [MHz]
Figure 1.21.7 f(XIN)-ICC Characteristics (at System Operating in High-Speed Mode)
Conditions: System operates at 25 C, with a ceramic resonator in medium-speed mode 3.0
Power source current ICC [mA]
2.0
1.0 : VCC = 5 V (During A-D conversion) : VCC = 5 V (No A-D conversion) : VCC = 3 V (During A-D conversion) : VCC = 3 V (No A-D conversion) 0.0
0.0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0
Clock input oscillation frequency f(XIN) [MHz]
Figure 1.21.8 f(XIN)-ICC Characteristics (at System Operating in Medium-Speed Mode)
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1.21.4 Typical Characteristics of Ports The typical characteristics of the ports described in this section are based on limited numbers of samples in the 7480 Group and 7481 Group. `Typical values' are not guaranteed. For the limits, refer to Section 1.21.1 Electrical Characteristics. Figure 1.21.9 shows measurement circuits of typical port characteristics. Figures 1.21.10 through 1.21.12 show the typical characteristics of ports of the 7480 Group and 7481 Group.
1
2 IOL - VOL characteristics IOH - VOH characteristics measurement circuit measurement circuit 7480 Group 7480 Group VCC 7481 Group 7481 Group VCC VCC IOL P00 IOH VSS 0 V to VCC P00
3
VCC
IIL - VIL characteristics measurement circuit 7480 Group 7481 Group
VCC
VCC
0 V to VCC
0 V to VCC
A
A
P00 IIL VSS VSS
A
Figure 1.21.9 Measurement Circuits of Typical Port Characteristics
Condition : 25 C -60.0
HIGH output current IOH [mA]
-50.0
-40.0 VCC = 5V -30.0
-20.0
-10.0
VCC = 3V
0.0 0.0 1.0 2.0 3.0 4.0 5.0
HIGH output voltage VOH [V]
Figure 1.21.10 VOH-IOH Characteristics on P-Channel Side of Programmable I/O Port (CMOS Output)
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70.0
Condition : 25 C
60.0
VCC = 5V
LOW output current IOL [mA]
50.0
40.0
30.0 VCC = 3V 20.0
10.0
0.0 0.0 1.0 2.0 3.0 4.0 5.0
LOW output voltage VOL [V]
Figure 1.21.11 VOL-IOL Characteristics on N-Channel Side of Programmable I/O Port (CMOS Output)
Condition : 25 C -0.6
-0.5
LOW input current IIL [mA]
-0.4
VCC = 5V
-0.3
-0.2 VCC = 3V -0.1
0.0 0.0 1.0 2.0 3.0 4.0 5.0
LOW input voltage VIL [V]
Figure 1.21.12 VIL-IIL Characteristics of Pull-up Transistor of Programmable I/O Port (CMOS Output)
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1.21.5 Typical Characteristics of A-D Conversion Figures 1.21.13 and 1.21.14 show typical characteristics of A-D conversion of the 7480 Group and 7481 Group in different measurement conditions. The bottom line in each graph shows an absolute accuracy error (ERROR), indicating offset from the ideal value at the point where an output code changes. For example, a `3F164016' change in an output code ideally takes place at the point where IN0 = 1270mV, in Figure 1.21.13. However, 1270-1 = 1269 mV is obtained as the measured changing point, because the absolute accuracy error is -1 mV. The top line in each graph represents the width of input voltages that have the same output code in 1-LSB WIDTH. For example, `21-20 = 1 mV (0.05 LSB)' is obtained as the differential non-linear error because the measurement value of the width of input voltages whose output codes are `3F16', is 21 mV.
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Figure 1.21.13 Typical Characteristics of A-D Conversion (1)
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Figure 1.21.14 Typical Characteristics of A-D Conversion (2)
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CHAPTER 2 APPLICATIONS
2.1 Input/Output Pins 2.2 Timer X and Timer Y 2.3 Serial I/O 2.4 A-D Converter 2.5 Reset 2.6 Oscillation Circuit 2.7 Power-Saving Function 2.8 Countermeasures against Noise 2.9 Notes on Programming 2.10 Differences between 7480 and 7481 Group, and 7477 and 7478 Group 2.11 Application Circuit Examples
APPLICATIONS
2.1 Input/Output Pins
2.1 Input/Output Pins
(1) External Circuit Example for Output Ports POINT: The following currents and voltages must be within specifications in the recommended operating conditions when external circuits for I/O ports are designed. For Input Ports Input voltage Input current For Output Ports Output sum currents Output peak current Output average current For the recommended operating conditions, refer to Section 1.21 Electrical Characteristics. Note: When a key matrix is used for multi-key inputs, take account of the total current which results from multiple inputs and is input to one port.
Figure 2.1.1 shows an external circuitry for output ports.
VCC=5 V * LOW output sum current IOL0 + IOL1 + IOL2 = 36 mA < 60 mA
(Note 1)
P00
IOL0=12 mA R0=250
(Note 1)
* LOW output peak current IOL0 = IOL1 = IOL2 = 12 mA < 20 mA * LOW output average current (in a period of 100 ms) (Note 2)
(Note 1)
P01
IOL1=12 mA R1=250
P02
IOL2=12 mA R2=250
12 mA x 10 ms x 5 = 6 mA < 10 mA 100 ms
Shaded areas: Maximum ratings
7480 Group 7481 Group
Notes 1: LED (VF = 2 V) used. 2: Turn-on timing of LEDs connected to port pins P00, P01 and P02 (50% duty cycle).
10 ms 10 ms Turned on for 10 ms, five times in a 100-ms period.
Figure 2.1.1 External Circuit for Output Ports
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APPLICATIONS
2.1 Input/Output Pins
(2) Simplifying External Circuit Example by Using Level Shift Port and Noise Margin POINT: Ports P4 and P5 have N-channel open-drain outputs. Built-in clamping diodes allow voltages VCC or more to be applied to port pins when the current for a pin is 1 mA or less. Voltages VIL = 0.4 VCC and VIH = 0.8 VCC can be applied to ports P3, P4, and P5 (at VCC = 4.5 V 5.5 V). Figure 2.1.2 shows a simplified external circuit example by using a level shift port and noise margin.
The former hardware
12 V power source (VCC) 5 V power source
SW
VI
Port
7480 Group 7481 Group
Hardware using level shift port
12 V power source (VCC)
SW Port VF VIL
Ground voltage level Max. 1.0 V
7480 Group 7481 Group
VIL = SW ground voltage level (Max.) + VF (Max.) = 1.0 [V] + 1.0 [V] = 2.0 [V] (Max.) 0.4 VCC
Figure 2.1.2 Simplified External Circuit Example by Using Level Shift Port and Noise Margin
7480 Group and 7481 Group User's Manual
2-3
APPLICATIONS
2.2 Timer X and Timer Y
2.2 Timer X and Timer Y
2.2.1 Application Example of Timer Mode Generation of period of 100 ms (100-ms Periodic Processing) POINT: The clock is divided by timer X, and the CPU performs periodic processing with a timer X interrupt service routine generated every 100 ms. SPECIFICATIONS: Clock: f(XIN) = 8 MHz A timer X interrupt is generated every 100 ms using the timer mode of timer X. Periodic processing is performed every 100 ms with timer X interrupt service routine.
Figure 2.2.1 shows a setting example of the division ratio. Figure 2.2.2 shows a control procedure example of 100-ms processing.
Fixed division ratio
Timer X
f(XIN) = 8 MHz
1/16
1/50000
100 ms
100-ms periodic processing with timer X interrupt service routine
Figure 2.2.1 Setting Example of Division Ratio
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7480 Group and 7481 Group User's Manual
APPLICATIONS
2.2 Timer X and Timer Y
RESET (Note 1) Initialize SEI
Set timer X mode register
b7
1 0 x x 0 0 0 0 TXM(Address 00F616) Timer * event count mode Writing to latch and timer simultaneously Timer X count source: f(XIN)/16 Timer X C34F16 (Note 2)
b0
Timer X interrupt request bit 0 Timer X interrupt enable bit 1 Set Timer XY control register
b7 b0
0 TXYCON(Address 00F816) Timer X count started CLI Timer X interrupt generated every 100 ms
Timer X interrupt service routine
Processing
100-ms periodic processing
RTI
Notes 1: State after system is released from reset * Timer X stop control bit = 1 (count stopped) 2: * C34F16 = 50000 - 1 * Write in order of low-order to high-order byte.
Figure 2.2.2 Control Procedure Example of 100-ms Processing
7480 Group and 7481 Group User's Manual
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APPLICATIONS
2.2 Timer X and Timer Y
2.2.2 Application Example of Event Count Mode Measurement of Water Flow Rate POINT: Pulses generated corresponding to the water flow rate are counted for a fixed period (100 ms), and the water flow rate during this period is calculated. SPECIFICATIONS: Clock: f(XIN) = 8 MHz Pulses generated corresponding to the water flow rate are input to the CNTR1 pin and counted using the event count mode of timer Y. The contents of timer Y are read in the timer X interrupt service routine generated after 100 ms from the start of counting pulses, and the water flow rate during 100 ms is calculated.
Figure 2.2.3 shows a peripheral circuit example. Figure 2.2.4 shows the method of measuring water flow rate. Figure 2.2.5 shows the control procedure example of measuring water flow rate. For the setting example of division ratio from timer X, refer to Figure 2.2.1.
7480 Group 7481 Group
Water flow rate sensor
Water flow
P41/CNTR1
Blades rotate in proportion to The faster the water flow, water flow and generate pulses. the shorter the pulse period.
Figure 2.2.3 Peripheral Circuit Example
100 ms
Timer X interrupt request bit
CNTR1 input Timer Y counting (Note).
Timer X, timer Y start counting.
Timer X interrupt service routine * Timer X, timer Y stop counting. * Timer Y is read out. Note: Counting rising edges.
* Flow rate during 100 ms = (FFFF16 - read value of timer Y) x flow rate per pulse
Figure 2.2.4 Method of Measuring Water Flow Rate
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7480 Group and 7481 Group User's Manual
APPLICATIONS
2.2 Timer X and Timer Y
Flow rate measuring routine
Timer X interrupt enable bit 0 Timer Y interrupt enable bit 0 Set timer XY control register
b7 b0
1 1 TXYCON(Address 00F816) Timer X count stop Timer Y count stop Port P41 (alternative function of CNTR1) is set to input. CNTR1 edge selection bit 0 (counting rising edges) Set timer X mode register
b7 b0
1 0 x x 0 0 0 0 TXM(Address 00F616) Timer * event count mode Writing to latch and timer simultaneously Timer X count source: f(XIN)/16 Set timer Y mode register
b7 b0
1 1 x x 0 0 0 0 TYM(Address 00F716) Timer * event count mode Writing to latch and timer simultaneously Timer Y count source: CNTR1 pin input Timer Y FFFF16 (Note 1) Timer X C34F16 (Note 2) Timer X interrupt request bit 0 Timer Y interrupt request bit 0 Timer X interrupt enable bit 1 Set timer XY control register
b7 b0
Timer X interrupt service routine
Set timer XY control register
b7 b0
1 1 TXYCON(Address 00F816) Timer X count stop Timer Y count stop Timer Y is read out (Note 3).
0 0 TXYCON(Address 00F816) Timer X count start Timer Y count start
END
RTI
Note 1: * Initial value. * Write to timer Y in order of low-order to high-order byte. 2: * C34F16 = 50000 - 1. * Write to timer X in order of low-order to high-order byte. 3: * (FFFF16 - the read value of Timer Y) = the number of CNTR1 edges detected during 100 ms. * Read from timer Y in order of high-order to low-order byte.
Figure 2.2.5 Control Procedure Example of Measuring Water Flow Rate
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APPLICATIONS
2.2 Timer X and Timer Y
2.2.3 Application Example of Pulse Output Mode Piezoelectric Buzzer Output POINT: The pulse output mode of a 16-bit timer is used for buzzer output. SPECIFICATIONS: Clock: f(XIN) = 8 MHz 4 kHz pulses are output from the CNTR0 pin using the pulse output mode of timer X. CNTR0 pin output level is fixed to HIGH while the buzzer output is stopped.
Figure 2.2.6 shows a peripheral circuit example. Figure 2.2.7 shows a setting example of the division ratio. Figure 2.2.8 shows a control procedure example of buzzer output.
7480 Group 7481 Group CNTR0 pin
P40/CNTR0 Buzzer output
Outputs HIGH level while buzzer output is stopped.
125 s 125 s Set the division ratio to make the timer X underflow period 125 s.
Figure 2.2.6 Peripheral Circuit Example
Fixed division
Timer X
f(XIN)=8MHz
1/8
1/125
125 s
1/2
250 s
CNTR0 pin outputs 4-kHz pulses.
Pulse output mode inverts the output level of the CNTR0 pin.
Figure 2.2.7 Setting Example of Division Ratio
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APPLICATIONS
2.2 Timer X and Timer Y
RESET(Note 1) Initialize SEI
Port P40 (alternative function of CNTR0) HIGH Port P40 (alternative function of CNTR0) is set to output. CNTR0 edge selection bit 0 (Note 2)
b7
Set timer X mode register 0 1 x x 0 0 0 1 TXM(Address 00F616) Pulse output mode Writing to latch and timer simultaneously Timer X count source : f(XIN)/8 Timer X 007C16(Note 3)
b0
CLI
Processing Buzzer output processing Buzzer output requested ? Y N Timer X count stopped ? Y Set timer XY control register
b7 b0
N N Timer X count operating ? Y Set timer XY control register
b0
b7
1 TXYCON(Address 00F816) Timer X count stop
0 TXYCON(Address 00F816) Timer X count start Timer X 007C16 (Note3)
Processing
Notes 1: State after system is released from reset * Timer X stop control bit = 1 (count stop) 2: In pulse output mode, the output level of CNTR0 pin is initialized to HIGH by writing to timer X (writing to latch and timer simultaneously). 3: * 007C16 = 125-1 * Write to timer X in order of low-order to high-order byte. * The output level of CNTR0 pin is initialized by writing to timer X (writing to latch and timer simultaneously).
Figure 2.2.8 Control Procedure Example of Buzzer Output
7480 Group and 7481 Group User's Manual
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APPLICATIONS
2.2 Timer X and Timer Y
2.2.4 Application Example of Pulse Period Measurement Mode Phase Control of Load (Measuring Period of Feedback Signal) POINT: The period of the feedback signal input from the load is measured using the pulse period measurement mode of a 16-bit timer. SPECIFICATIONS: Clock: f(XIN) = 8 MHz Phase control signal is output to the load and controls the load's phase. The period of the feedback signal input to the CNTR0 pin from the load is measured using the pulse period measurement mode of timer X. * Count source: f(XIN)/16 The period of the feedback signal is analyzed to adjust the phase control signal input to the load.
For the output of the phase control signal, refer to Section 2.2.7 Application Example of Programmable One-shot Output Mode. Figure 2.2.9 shows a peripheral circuit example. Figure 2.2.10 shows a phase control procedure example.
7480 Group 7481 Group Feedback signal
Load
Phase control signal
P40/CNTR0
Port
VAC
Figure 2.2.9 Peripheral Circuit Example
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7480 Group and 7481 Group User's Manual
APPLICATIONS
2.2 Timer X and Timer Y
RESET(Note 1) Initialize SEI
Port P40 (alternative function of CNTR0) is set to input. CNTR0 edge selection bit 0 (measuring a period from rising until the next rising edge)
Set timer X mode register
b7 b0
1 0 x x x 0 1 0 TXM(Address 00F616) Pulse period measurement mode Timer X count source: f(XIN)/16
CNTR0 interrupt request bit 0 CNTR0 interrupt enable bit 1 Set timer XY control register
b7 b0
0 TXYCON(Address 00F816) Timer X count start CLI When detecting rising edge input to CNTR0 pin Processing Phase control processing * Period of feedback signal analyzed * Phase control signal adjusted Processing CNTR0 interrupt service routine
Timer X is read out (Note 2).
END
Notes 1: State after system is released from reset * Timer X stop control bit = 1 (count stop) * Timer X interrupt enable bit = 0 (disabled) 2: Read from timer X in order of high-order to low-order byte.
Figure 2.2.10 Phase Control Procedure Example
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APPLICATIONS
2.2 Timer X and Timer Y
2.2.5 Application Example of Pulse Width Measurement Mode Communications between Two Microcomputers (Reception) POINT: 8-bit data is received by measuring each bit's HIGH-level width input to the CNTR pin and identifying each bit data. SPECIFICATIONS: Clock: f(XIN) = 8 MHz The HIGH-level width of CNTR0 pin input is measured using the pulse width measurement mode of timer X. * Count source: f(XIN)/8 The start, stop bits and each bit data of 8-bit receive data are identified by the measured values of the HIGH-level widths.
Figure 2.2.11 shows a peripheral circuit example. Figure 2.2.12 shows a communication format example. Figure 2.2.13 shows a communication control procedure example.
7480 Group 7481 Group (Receiver)
Microcomputer (transmit ter)
Data
P40/CNTR0
Figure 2.2.11 Peripheral Circuit Example
Start pulse
8-bit data
D0=0 D1=1 0.35 ms D2=0 D7=1 0.35 ms
Stop pulse
0.55 ms 0.05 ms
0.15 ms
0.15 ms
0.75 ms
Longest communication time 4.6 ms Shortest communication time 3.0 ms
Data pulse`0': HIGH level output for 0.15 ms Data pulse`1': HIGH level output for 0.35 ms Start pulse: HIGH level output for 0.55 ms Stop pulse: HIGH level output for 0.75 ms (The LOW levels are output for 0.05 ms or more before and after each pulse.)
Figure 2.2.12 Communication Format Example
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APPLICATIONS
2.2 Timer X and Timer Y
RESET(Note 1) Initialize SEI
Port P40 (alternative function of CNTR0) is set to input. CNTR0 edge selection bit 0(HIGH width measured)
Set timer X mode register
b7
0 1 x x x 0 1 1 TXM(Address 00F616) Pulse width measurement mode Timer X count source: f(XIN)/8 Timer X interrupt service routine processing Timer X interrupt request bit 0 CNTR0 interrupt request bit 0 Timer X interrupt enable bit 1 CNTR0 interrupt enable bit 1 Error-recovery processing
b0
Set timer XY control register
b7 b0
RTI
0 TXYCON(Address 00F816) Timer X count start CLI
C : Carry Flag rDATA : RAM for received data (1 byte) rWORK : RAM for receiving data (2 bytes) rCOUNT : RAM for counting data (1 byte) Notes 1: After system is released from reset * Timer X stop control bit = 1 (count stopped) * CNTR0 edge selection bit = 0 (HIGH pulse width measured) * Pin P40/CNTR0: input mode 2: Read from timer X in order of high-order to low-order byte. 3: 100 to 199 (Data pulse `0') 4: 300 to 399 (Data pulse `1') 5: 500 to 599 (Start pulse) 6: 700 to 799 (Stop pulse)
RTI
CNTR0 interrupt service routine
Timer X is read out (Note 2). Read value from timer X ?
006416 through 00C716 (Note 3) 012C16 through018F16 (Note 4)
01F416 through 025716 (Note 5)
02BC16 through 031F16 (Note 6)
Others
C0 ROR rWORK
b7
C1
rWORK0016 rCOUNT0016
rCOUNT = 8 ? Y rDATArWORK
N
b0
C rWORK(Internal RAM) rCOUNTrCOUNT + 1
Processing against error generation
RTI
Figure 2.2.13 Communications Control Procedure Example
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APPLICATIONS
2.2 Timer X and Timer Y
2.2.6 Application Example of Programmable Waveform Generation Mode Control of Motorcycle Single-Cylinder Engine POINT: A trigger input to the INT pin automatically starts a timer counting. This allows the CNTR pin output to be changed with a more accurate timing than counting is started in an INT interrupt service routine. SPECIFICATIONS: Clock: f(XIN) = 8 MHz A rise-to-rise period of a crank angle signal input to the CNTR0 pin is measured using the pulse period measurement mode of timer X to determine the correction value of timer Y. The trigger of the crank angle signal input to the INT1 pin makes timer Y activated. Then, the control signal of the igniter is output from the CNTR1 pin using the programmable waveform generation mode.
For the pulse period measurement of the crank angle signal, refer to Section 2.2.4 Application Example of Pulse Period Measurement Mode. Figure 2.2.14 shows a peripheral circuit example. Figure 2.2.15 shows an operation timing example. Figure 2.2.16 shows a control procedure example of motorcycle engine.
7480 Group 7481 Group Motorcycle single-cylinder engine
Igniter Crank angle input Phase control signal P41/CNTR1 P40/CNTR0 P31/INT1
Figure 2.2.14 Peripheral Circuit Example
Timer Y activated INT1 pin input CNTR0 pin input (Crank angle signal)
Contents of timer Y
Timer Y activated
Timer Y activated
T
RL RL Initial value 000016 UF UF UF RL
TL0 set 1 TL1set 2 RL RL Count stop 5 Initial value set 6 RL RL
UF 3
UF 4
UF
UF
Timer Y output level latch CNTR1 pin output (Igniter control signal)
UF : Underflow RL : Reload
T : Measured with pulse period measurement mode of timer X TL0 : The written value to timer Y to correct HIGH output time of the CNTR1 pin (determined by measured value T). TL1 : The written value to timer Y to output LOW time of the CNTR1 pin (determined by measured value T).
Figure 2.2.15 Operation Timing Example 2-14
7480 Group and 7481 Group User's Manual
APPLICATIONS
2.2 Timer X and Timer Y
RESET(Note 1) Initialize SEI
INT1 Interrupt service routine
Change timer Y (Note 3)
Port P40 (alternative function of CNTR0) is set to input. Port P41 (alternative function of CNTR1) is set to output. INT1 edge selection bit (rising edge detected) CNTR0 edge selection bit (rise-to-rise period detected)
RTI
Timer Y interrupt service routine
Set timer X mode register
b7
After INT1 edge detected, first timer Y interrupt occurs?
N
x x x 0 1 0 TXM(Address 00F616) Pulse period measurement mode Timer X count source selected
b0
Y
Change timer Y (Note 3) Change timer Y output level latch
b7 b0
Set timer Y mode register (Note 2)
b7 b0
1 0 1 1 0 0 TYM (Address 00F716) Output level latch
1 1 0 1 0 0 TYM (Address 00F716) Programmable waveform generation mode Writing to latch and timer simultaneously Output level latch Timer Y activated by input signal to INT1 pin Timer Y count source selected Timer Y Initial value (Note 3) Control timer Y writing
b7 b0
After INT1 edge detected, second timer Y interrupt occurs?
N
Y
Change timer Y output level latch
b7 b0
1 1 1 1 0 0 TYM (Address 00F716) Output level latch
1 1 1 1 0 0 TYM (Address 00F716) Writing to latch only Set timer XY control register
b7 b0
After INT1 edge detected, third timer Y interrupt occurs?
N
Y
Stop timer Y counting
b7 b0
0 0 TXYCON (Address 00F816) Timer X count start Timer Y count start (Note 4)
1 0 TXYCON (Address 00F816) Timer Y count stop Control timer Y writing
b7 b0
Timer Y interrupt request bit 0 INT1 interrupt request bit 0 Timer Y interrupt enable bit 1 INT1 interrupt enable bit 1 CLI
1 1 0 1 0 0 TYM (Address 00F716) Writing to latch and timer simultaneously Timer Y Initial value (Note 3) Control timer Y writing
b7 b0
111100
TYM (Address 00F716) Writing to latch only
Start Timer Y counting Processing
b7 b0
0 0 TXYCON (Address 00F816) Timer Y count start (Note 4)
Notes 1: State after system is released from reset * Timer X and Y stop control bits = 0 (count stopped) * Timer Y and INT1 interrupt enable bits = 0 (disabled) 2: The output level of CNTR1 pin is initialized to LOW. 3: Write to timer Y in order of low-order to high-order byte. 4: In this time, timer Y remains still stopped.
RTI
Figure 2.2.16 Control Procedure Example of Motorcycle Engine
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APPLICATIONS
2.2 Timer X and Timer Y
2.2.7 Application Example of Programmable One-Shot Output Mode Phase Control of Load (Output of Phase Control Signals) POINT: The phase control signal to the load is output using the programmable one-shot output mode of a 16-bit timer. SPECIFICATIONS: Clock: f(XIN) = 8 MHz The phase control signal to the load is output from the CNTR1 pin using the programmable one-shot output mode of timer Y. * Count source: f(XIN)/16 * Rising edges of the signal input to the INT1 pin from the trigger detection circuit are detected. * A triac is turned on at the HIGH level. The period of the feedback signal input from the load is measured, analyzed, and used to adjust the phase control signal.
For the measurement of the period of the feedback signal, refer to Section 2.2.4 Application Example of Pulse Period Measurement Mode. Figure 2.2.17 shows a peripheral circuit example. Figure 2.2.18 shows an operation timing example. Figure 2.2.19 shows a phase control procedure example.
7480 Group 7481 Group Feedback signal
Load
Phase control signal
Port
P41/CNTR1
Trigger detection circuit VAC
P31/INT1
Figure 2.2.17 Peripheral Circuit Example
VAC power supply INT1 pin input
Contents of timer Y
Writing to latch in timer Y interrupt service routine RL RL RL RL RL RL RL RL RL RL RL RL
000016
UF
UF
UF
UF
UF
UF
CNTR1 pin output
Figure 2.2.18 Operation Timing Example
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APPLICATIONS
2.2 Timer X and Timer Y
RESET(Note 1) Initialize SEI
INT1 interrupt service routine
Change timer Y (Note 3) Port P41 (alternative function of CNTR1) LOW RTI Port P41 (alternative function of CNTR1) is set to output. INT1 edge selection bit 1 (rising edge detected) CNTR1 edge selection bit 0 (Note 2)
Set timer Y mode register
b7 b0
1 0 x x 1 1 0 1 TYM(Address 00F716) Programmable one-shot output mode Writing to latch only Timer Y count source : f(XIN)/16 Timer Y Initial value (Note 3) Set timer XY control register
b7 b0
0
TXYCON(Address 00F816) Timer Y count start
INT1 interrupt request bit 0 INT1 interrupt enable bit 1 CLI
Processing
Phase control processing * Period of feedback signal measured * Measured value analyzed (determination of timer Y setting value)
Processing
Notes 1: State after system is released from reset * Timer Y stop control bit = 0 (count stop) * Timer Y interrupt enable bit = 0 (disabled) 2: HIGH level one-shot pulse is output. 3: Write to timer Y in order of low-order to high-order byte.
Figure 2.2.19 Phase Control Procedure Example
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APPLICATIONS
2.2 Timer X and Timer Y
2.2.8 Application Example of PWM Mode Output of Analog Voltage POINT: Analog voltage is output using the PWM waveform. SPECIFICATIONS: Clock: f(XIN) = 8 MHz PWM waveforms are output from the CNTR0 pin using the PWM mode of timer X. * Count source: f(XIN)/16 * The duty cycle of PWM waveforms is determined depending on analog voltage output. PWM waveforms are converted into the analog voltage using the external circuit to the CNTR0 pin.
Figure 2.2.20 shows a peripheral circuit example. Figure 2.2.21 shows a control procedure example of analog voltage output.
7480 Group 7481 Group
HH VCC VSS P40/CNTR0 VCC x HL VCC HH HH+HL VSS
Figure 2.2.20 Peripheral Circuit Example
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APPLICATIONS
2.2 Timer X and Timer Y
Analog voltage output routine
Set timer XY control register
b7 b0
1 TXYCON(Address 00F816) Timer X count stop Set port P40 (alternative function of CNTR0) (Note). Port P40 (alternative function of CNTR0) is set to output. Set Timer X Mode Register
b7
x x 0 1 1 0 TXM(Address 00F616)
PWM mode Writing to latch and timer simultaneously Timer X count source selected Set Timer X low-order byte (LOW width) Set Timer X high-order byte (HIGH width)
b0
Set Timer XY Control Register
b7 b0
0 TXYCON(Address 00F816) Timer X count start
END
Note: The output analog voltage is initialized (VSS or VCC). * The same potential as VSS to be output : P40/CNTR0 pin is set to `0'. * The same potential as VCC to be output : P40/CNTR0 pin is set to `1'.
Figure 2.2.21 Control Procedure Example of Analog Voltage Output
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APPLICATIONS
2.3 Serial I/O
2.3 Serial I/O
2.3.1 Application Example of Clock Synchronous Serial I/O Transmission Successive Transmission POINT: Successive transmission is performed by generating a serial I/O transmit interrupt when the transmit buffer register is emptied, as well as by generating a serial I/O transmit interrupt request when serial I/O transmission is initialized to `enable' by using the serial I/O control register (Note). Note: Refer to Using Serial I/O Transmit Interrupt and Serial I/O Receive Interrupt of (5) Notes on Usage of Clock Synchronous Serial I/O in Section 1.14.2 Clock Synchronous Serial I/O. SPECIFICATIONS: Clock: f(XIN) = 7.9872 MHz 5-byte successive transmission using clock synchronous serial I/O * Baud rate: 2400 bps * Synchronous clock: a frequency of 2.4 kHz, obtained from dividing f(XIN) is output from the SCLK pin. * The completion of communication preparation at the receiver is recognized using port pin P17 as the SRDY signal input pin.
Figure 2.3.1 shows a connections example. Figure 2.3.2 shows a setting example of the synchronous clock. Figure 2.3.3 shows the timing of interrupt control. Figure 2.3.4 shows a control procedure example of serial I/O transmit.
P15/TxD P16/SCLK P17/SRDY
RxD SCLK SRDY
7480 Group 7481 Group
Microcomputer (Receiver)
Figure 2.3.1 Connection Example
f(XIN) = 7.9872 MHz
1/4
BRG count source selection bit `0'
Baud rate generator
1/52
BRG output
1/4
1/4
`1'
Clock generator
Synchronous clock 2.4 kHz
Baud rate : 2400bps
Figure 2.3.2 Setting Example of Synchronous Clock
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APPLICATIONS
2.3 Serial I/O
Setting of serial I/O control register
1st byte transmitted 3rd byte transmitted
5th byte transmitted
1st byte transmitted 2nd byte transmitted
2nd byte transmitted 4th byte transmitted
Serial I/O transmit interrupt request bit Serial I/O transmit interrupt enable bit
Undefined
ABA Write `1' Execute CLI instruction
BA
BA
BA B Write `0'
A Write `1'
BA
Transmission requested
5-byte transmission completed
Transmission requested
Interrupt disable flag
System is released from reset.
: Processed within serial I/O transmit interrupt service routine. A : Cleared by the acceptance of serial I/O transmit interrupt request. B : Interrupt request generated with transmitter buffer register emptied.
Figure 2.3.3 Timing of Interrupt Control
RESET(Note 1) Initialize SEI
Serial I/O transmit interrupt service routine
Port P17 = LOW ? Port P17 is set to input. Baud rate generator 3316 (Note 2) Set serial I/O control register (Note 3)
b7 b0
N
Y Transmit buffer register BUFF_p(Note 4) 1 is added to pointer p for BUFF. pp+1
1 1 0 1 0 0 0 1 SIOCON (Address 00E216) BRG count source: f(XIN)/16 Synchronous clock: BRG output divided by 4 SRDY output disabled Transmit interrupt source: Transmission buffer register is empty. Transmit enabled Receive disabled Clock synchronous serial I/O Serial I/O enabled
p5? Y Serial I/O transmit interrupt enable bit 0
N
RTI CLI Transmit processing 5-byte transmission data is stored to buffer area (BUFF) BUFF_0 Transmission data 0 BUFF_1 Transmission data 1 *** BUFF_4 Transmission data 4 (1st byte) Initialize pointer p for BUFF p0 Serial I/O transmit interrupt enable bit 1 Serial I/O transmit interrupt
Processing
Transmission requested ? N
Y
Processing
Notes 1: State after system is released from reset * Serial I/O transmit interrupt enable bit = 0 * Serial I/O receive interrupt enable bit = 0 2: 3316 = 52-1 3: In this time, serial I/O transmit interrupt request bit is 1. 4: Transmit/receive is started by writing to transmit buffer register.
BUFF: 5-byte buffer area BUFF_0 to BUFF_4
Figure 2.3.4 Control Procedure Example of Serial I/O Transmit
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APPLICATIONS
2.3 Serial I/O
2.3.2 Application Example of Clock Asynchronous Serial I/O (UART) Reception Processing of Received Data Bytes as a Packet POINT: RAM area is secured by adding the several bytes to the maximum number of bytes necessary for data processing, and the received data is stored in increasing order of address in the interrupt service routine. If the data overflows the RAM area, the overflow data is stored at the start address of the RAM. When the received data whose byte number satisfies the requirement of data processing is stored completely in the buffer area, the data processing is performed in the main routine. As a result, the received data can be stored without losing any bits of data in process even when the subsequent received data is stored completely during the data processing. SPECIFICATIONS: Clock: f(XIN) = 7.9872 MHz UART reception * Baud rate : 9600 bps * Synchronous clock : f(XIN) is divided into 9.6 kHz * Communication format: 1ST-8DATA-1SP Processing received data as a packet The head data of every packet consists of the code characteristic for the head data and the code indicating the number of bytes of the packet.
Figure 2.3.5 shows a connection example. Figure 2.3.6 shows the setting example of the synchronous clock. Figure 2.3.7 shows a communication format. Figure 2.3.8 shows a control procedure example of serial I/O receive.
TxD
P14/RxD
Microcomputer (Transmitter)
7480 Group 7481 Group (Receiver)
Figure 2.3.5 Connection Example
f(XIN) = 7.9872 MHz
1/4
BRG count source selection bit `0'
Baud rate generator
1/13 1/4
`1'
BRG output
1/16
Clock generator
Synchronous clock 9.6 kHz
Baud rate : 9600bps
Figure 2.3.6 Setting Example of Synchronous Clock
Transmit data (1ST-8DATA-1SP)
LSB MSB
ST
D0
D1
D6 1st byte
D7
SP (n - 1)th byte
Head data
ST: Di: SP: N:
Start bit Data bit (i = 0 to 7) Stop bit The number of bytes of the packet
: Consists of the code characteristic for the head data
and the code indicating the number of bytes of the packet.
1 packet (N bytes)
Figure 2.3.7 Communication Format
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APPLICATIONS
2.3 Serial I/O
RESET (Note 1) Initialize SEI BUFF_0 Pointer for writing to BUFF (pw) 0016 Pointer for reading from BUFF (pr) 0016 Baud rate generator 0C16 (Note 2) Set serial I/O control register
b7
RAM area
BUFF_1
BUFF_pw
Write receive data in serial I/O receive interrupt service routine
1 0 1 0 x x 0 0 SIOCON (Address 00E216) BRG count source : f(XIN)/4
Synchronous clock : BRG output divided by 16
b0
BUFF_pr
Head data of the packet
Transmit disabled Receive enabled Clock asynchronous serial I/O Serial I/O enabled Set UART control eegister
b7 b0
BUFF_(N-2) BUFF_(N-1)
N-byte buffer area
0 x 0 0 UARTCON (Address 00E316) Character length bit : 8 bits Parity disabled Stop bit length : 1 bit Serial I/O receive interrupt service routine
Read from receive buffer register Serial I/O receive interrupt request bit 0 Serial I/O receive interrupt enable bit 1 CLI Processing head data received? Y Analyze the number of bytes of the packet Processing i 0016 pr pw and i = the number of bytes of the packet ? Y * The contents of pr and data of the numbers of bytes packet is stored in another RAM in order not to destroy them. * Processing for 1 packet data from BUFF_pr i 0016 pr = pw N pr = pw BUFF_pw Read data
N
ii+1 pr pr + 1 N
pr N? Y pr 0016
Processing RTI
Notes 1: Processing after system is released from reset. *Serial I/O receive interrupt enable bit = 0 (disabled) 2: 0C16 = 13-1
Figure 2.3.8 Control Procedure Example of Serial I/O Receive
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APPLICATIONS
2.3 Serial I/O
2.3.3 Application Example of Bus Arbitration Interrupt LAN Communications in Contention Bus System POINT: In LAN communications with the contention bus system, the malfunction of transmission due to bus collision is detected with a bus arbitration interrupt. SPECIFICATIONS: Clock: f(XIN) = 7.9872 MHz LAN communication format: Simplified SAE J1850 (PWM system) The CNTR0 pin is connected to the RxD pin, and SOF is detected with the rising edge of a CNTR0 pin input Data is transmitted and received by clock synchronous serial I/O communications. * Baud rate: 41600 bps * Synchronous clock: f(XIN) is divided into 41.6 kHz * Bus collision detected The HIGH level has priority on LAN communication line at bus collision
Figure 2.3.9 shows a connection example. Figure 2.3.10 shows a setting example of the synchronous clock. Figure 2.3.11 shows a communication format example of simple SAE J1850. Figure 2.3.12 shows a communication timing example. Figures 2.3.13 and 2.3.14 show control procedure examples.
Unit B
LAN communication Line (+) LAN communication Line (-)
Unit C
Unit D
Unit A
P15/TxD P14/RxD P40/CNTR0 IN OUT BUS + BUS -
* Conflicts between unit A and unit B Unit A TxD pin output Unit B TxD pin output LAN communication line (RxD pin input)
H L H L H L
Driver
7480 Group 7481 Group
Bus collision detected in unit B
Figure 2.3.9 Connection Example
f(XIN)=7.9872MHz
1/4
BRG count source selection bit `0'
Baud rate generator
1/3
BRG output
1/4
Clock generator
1/4
`1'
Synchronous clock 41.6 kHz
Baud rate : 41600bps
Figure 2.3.10 Setting Example of Synchronous Clock
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APPLICATIONS
2.3 Serial I/O
1 frame
1 byte Priority code 1 byte Target ID 1 byte Source ID Max. 7 bytes Data area 1 byte CRC code 1 byte RSP code
SOF
EOD
EOF
IFS
Transmit/Receive Data Name
Function
Transmission/Reception
SOF
Indicates the head of
(Start of Frame) the frame
* Fixed format of 6 time. * Transmitter transmits `001111002' with serial transmission. * Receiver detects data with CNTR0 interrupt and recognizes with pulse width measurement mode of timer X.
4 time
H L
2 time
When transmitting
Priority Code
Code for priority control in multi-unit transmission
* 1 bit represented by 3 time (1 byte represented by 3 bytes). * Both transmitter and receiver communicate with serial I/O. * Priority code: `0016' (high priority) through `FF16' (low priority).
3 time
H H L
3 time
H L
3 time
Target ID
ID number of target unit
L
Data
When transmitting `1'
Transmit data generated
When transmitting `0'
b7
Source ID Data Area CRC Code
Transmit data 1 0 D6 1
ID number of transmit unit Transmit data Code for error detection
1 byte data transmit
b7
b0
D5 1
b7
0 D7 1
b0
1 byte data
b0
Transmit data 2
D7 D6 D5 D4 D3 D2 D1 D0
1 0 D3 1 0 D4 1 0
b7
Transmit data 3 0 D1 1
b0
0 D0 1
0 D2
RSP Code
Receiver transmits self-address if data is correctly received on error detection
Transmit data 1
H L
Transmit data 2
Transmit data 3
D7
D6
D5
D4
D3
D2
D1
D0
EOD
(End of Data)
Indicates the end of data Indicates the end of frame Indicates the separation between frames
* Fixed format of 3 time. * Both transmitter and receiver generate a wait time with timer 1.
3 time
H L
EOF
(End of Frame)
IFS
(Inter-Frame Separation)
* Fixed format of 6 time. * Both transmitter and receiver generate a wait time with timer 1.
6 time
H L
Figure 2.3.11 Communication Format Example of Simplified SAE J1850
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2.3 Serial I/O
* When unit A, unit B, and unit C start transmitting simultaneously
Priority code `01xxxxxx2' 0 1
SOF
Target ID
Unit A TxD pin output
H L
Writing `0011110016' to transmit buffer register for SOF transmission
Bus collision detected Transmit processing completed Receive processing start
Successive writing dummy data `0016' to transmit buffer register for reception of target ID to CRC code
Receive processing completed after recognizing that target ID is not source ID of unit A.
SOF 0
Priority code `00xxxxxx2' 0
Target ID `1 xxxxxxx2' 1
EOD
RSP code
EOF
IFS
Unit B TxD pin output
H L
Writing `0011110016' to transmit buffer register for SOF transmission
Bus collision detected Transmit processing completed Receive processing start
Successive writing dummy data `0016' to transmit buffer register for reception of source ID to CRC code after recognizing that target ID is source ID of unit B.
When the correct reception is checked by CRC code, writing RSP code to transmit buffer register is performed.
Receive processing completed
SOF 0
Priority code `00xxxxxx2' 0
Target ID Source ID `0 xxxxxxx2' transmit data (Transmit to unit B) CRC code EOD 0
RSP code
EOF
IFS
Unit C TxD pin output
H L
Writing `0011110016' to transmit buffer register for SOF transmission
Successive writing 3 times dummy data `0016' to transmit buffer register for reception of RSP code
Transmit processing completed
Units other than units A, B and C start receive processing at the rising edge of CNTR0 pin SOF Priority code 0 0 0 Target ID
Source ID transmit data CRC code EOD
RSP code
EOF
IFS
LAN communication line (RxD pin input)
H L
Units other than units A, B and C write successively dummy data `0016' to transmit buffer register for reception of priority code to CRC code
Receive processing completed after recognizing that target ID is not source ID of units other than unit B.
Communication completed
Figure 2.3.12 Communication Timing Example
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2.3 Serial I/O
RESET(Note 1) Initialize SEI
Transmit service routine
Port P40 (alternative function of CNTR0 pin) is set to input. CNTR0 edge selection bit 1 (Rising edge active)
When transmit is started * Transmit data generated (1 byte represented by 3 bytes) * Bus arbitration interrupt request bit 0 * Bus arbitration interrupt enable bit 1 * CNTR0 interrupt enable bit 0 * SOF transmission (writing to transmit buffer register) When EOD is output, waiting time is generated (Note 3) After EOD waiting time elapses, RSP code is received (writing dummy data to transmit buffer register) After receiving RSP code, EOF and IFS are output and waiting time is generated (Note 3) After EOF/IFS waiting time elapses (when transmit completed) * Bus arbitration interrupt enable bit 0 * CNTR0 interrupt request bit 0 * CNTR0 interrupt enable bit 1
Baud rate generator 0216 (Note 2) Set serial I/O control register (Note 3)
b7 b0
1 1 1 1 0 0 0 1 SIOCON (Address 00E216) BRG count source: f(XIN)/16 Synchronous clock: BRG output divided by 4 SRDY output disabled Transmit interrupt source: Transmission buffer register is empty. Transmit enabled Receive enabled Clock synchronous serial I/O Serial I/O enabled
END Receive service routine
Bus collision detection enable bit 1 Serial I/O transmit interrupt request bit 0 Serial I/O receive interrupt request bit 0 CNTR0 interrupt request bit 0 Serial I/O transmit interrupt enable bit 1 Serial I/O receive interrupt enable bit 1 CNTR0 interrupt enable bit 1 CLI
After SOF receive is completed * CNTR0 interrupt enable bit 0 When priority code to CRC code, and RSP code are received 3-byte receive data is converted to 1-byte data. Receive processing is completed after recognizing that received target ID is not self ID. When EOD is detected, EOD waiting time is generated (Note 3) When the correct reception is checked by CRC code after EOD waiting time elapses, RSP code is transmitted (writing to transmit buffer register) After transmitting RSP code, EOF and IFS waiting time is generated (Note 3) After EOF/IFS wait time elapses (when receive completed) * CNTR0 interrupt request bit 0 * CNTR0 interrupt enable bit 1 END
Processing
During transmission or reception ? N Transmission requested ? N
Y During transmitting During receiving
Y
Transmit service routine
Receive service routine
Processing
Notes 1: State after system is released from reset * Bus arbitration interrupt enable bit = 0 2: 0216 = 3-1 3: Waiting time is generated by timer 1. 4: Write `0016' as dummy data to transmit buffer register.
Figure 2.3.13 Control Procedure Example (1) of LAN Communications
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APPLICATIONS
2.3 Serial I/O
Serial I/O transmit interrupt service routine
Serial I/O receive interrupt service routine
When transmitting Write the following transmit data to transmit buffer register by the byte at one interrupt processing 1. Priority code 2. Target ID 3. Source ID 4. Data 5. CRC code In the interrupt processing after writing transmit data to transmit buffer register is completed, change transmit interrupt source to `when transmit shift operation is completed', and the interrupt source is back to the state before changing at the next interrupt processing. When receiving Write dummy data to transmit buffer register
When transmitting Transmit data is received When RSP code is received When receiving Read receive buffer register 1. Priority code 2. Target ID 3. Source ID 4. Data 5. CRC code Level of RxD pin is checked every 3-byte reception * HIGH level: next data is received * LOW level: EOD is detected
RTI
RTI
Bus arbitration interrupt service routine
CNTR0 interrupt service routine (when receiving)
When SOF collision occurs, transmit processing is stopped and receive processing is started from priority code. When priority code collision occurs, transmit processing is stopped and receive processing is started from target ID. When data collision occurs, communication error on communication line is detected, transmit processing is stopped, and processing against error such as retransmission is performed. Bus arbitration interrupt enable bit 0
When rising edge is detected * CNTR0 edge selection bit 0 (falling edge detected) * HIGH width is measured with timer X When falling edge is detected * CNTR0 edge selection bit 1 (rising edge detected) * LOW width is measured with timer X * SOF LOW width waiting time is generated with timer 1 (acceptance of timer 1 interrupt request is enabled) Reception is completed when SOF is not received correctly.
RTI
RTI
Timer 1 interrupt service routine
When SOF is received * Write dummy data to transmit buffer register for generating synchronous clock * Acceptance of timer 1 interrupt request is disabled Processing for EOD, EOF and IFS waiting time elapse
RTI
Note: Write `0016' as dummy data to transmit buffer register.
Figure 2.3.14 Control Procedure Example (2) of LAN Communications
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2.4 A-D Converter
2.4 A-D Converter
2.4.1 Determination of A-D Conversion Values In A-D conversion, it is recommended to determine conversion values using several samplings to improve the accuracy of A-D conversion. Methods for sampling and determining A-D conversion values are described below. Sampling Methods EXAMPLES: Sampling 2 n times Running sampling 2n times Sampling (2 n + 2) times Notes 1: `n' is a positive integer according to the specifications. Determining Methods EXAMPLES: The sum of the sampling result is divided by the number of times of the sampling. Except the minimum and the maximum value, the sum of the sampling (or running sampling) results of (2 n + 2) times is divided by 2 n. The average value calculated by or is updated unless the difference between the previous and the newest value is `m' or more. Notes 2: `m' and `n' are positive integers according to the specifications. A method derived from these examples of sampling and determining is explained in Section 2.4.2 Application Example of A-D Converter.
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2.4 A-D Converter
2.4.2 Application Example of A-D Converter POINT: To improve the accuracy of A-D conversion, A-D conversion values are determined by Sampling Methods and , and Determining Methods and of Section 2.4.1 Determination of A-D Conversion Values. SPECIFICATIONS: After the running sampling has been taken 6 times, the sum of the sampling results, except the minimum and maximum values, is divided by 4. When the difference between the new average value and the previous updated value is less than 5, the value is updated to the new value, when 5 or more, the value is not updated.
Figure 2.4.1 shows the example of determining A-D conversion values. Figure 2.4.2 shows the control procedure example of determining of A-D conversion values.
The newest A-D conversion result
Sampling point A-D conversion result
(n-7)th sampling
(n-6)th sampling
(n-5)th sampling
(n-4)th sampling
(n-3)th sampling
(n-2)th sampling
(n-1)th sampling
n-th sampling
(n+1)th sampling
A816
A716
A916
A816
A616 Minimum value
A716
A816
AB16 Maximum value
Time
Average value =
A916 + A816 + A716 + A816 4
= A816
Figure 2.4.1 Example of Determining A-D Conversion Values
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2.4 A-D Converter
A-D conversion routine
A-D conversion completion interrupt request bit `0' Set A-D conversion control register
b7 b0
1 1 0 0 0 ADCON (Address 00D916) Analog input pin : P20/IN0 Connect between VREF pin and ladder resistor VREF stabilizing wait time Set A-D conversion control register
b7 b0
1 0 0 0 0 ADCON (Address 00D916) A-D conversion start
A-D conversion completed ? (Note) Y Average of 4-time samplings, which the maximum value and the minimum value are excluded from 6-time samplings, is calculated.
N
The difference from previous determined value is less than 5 ? Y Update of determined value (The last calculated average value becomes the determined value)
N
END
Note: The completion of A-D conversion is examined by the following. * A-D conversion completion bit of A-D conversion control register is `1'. * A-D conversion completion interrupt request bit of interrupt request register 1 is `1'. * Branch to A-D conversion completion interrupt service routine is performed. (When A-D conversion completion interrupt is enabled)
Figure 2.4.2 Control Procedure Example of Determining A-D Conversion Values
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2.5 Reset
2.5 Reset
Figure 2.5.1 shows reset circuit examples.
7480 Group 7481 Group
RESET
7480 Group 7481 Group VCC
RESET
VCC
Power source voltage detection circuit
RESET, VCC pin number
32pin RESET pin VCC pin 18 17 42pin 25 22 44pin 21 18
Figure 2.5.1 Reset Circuit Examples
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2.6 Oscillation Circuit
2.6 Oscillation Circuit
2.6.1 Oscillation Circuit with Ceramic Resonator An oscillation circuit can be formed by connecting a ceramic resonator between the XIN and XOUT pins. Figure 2.6.1 shows an oscillation circuit example with a ceramic resonator. Note: Set oscillation circuit parameters, such as Rd, CIN, and COUT, to the values recommended by the manufacturer of the resonator.
CIN
7480 Group 7481 Group
XIN XOUT
Rd
COUT
XIN, XOUT pin number
32pin XIN pin XOUT pin 14 15 42pin 19 20 44pin 14 15
Figure 2.6.1 Oscillation Circuit Example with Ceramic Resonator 2.6.2 External Clock Input to XIN An external clock input to the XIN pin can be supplied to the built-in clock generator. Figure 2.6.2 shows the external clock circuit example. Notes 1: Leave the XOUT pin open when an external clock is input to the XIN pin. 2: Use a 50% duty cycle pulse signal as the external clock input to the XIN pin.
7480 Group 7481 Group
XIN XOUT
Open External clock VCC VSS Duty cycle 50%
XIN, XOUT pin number
32pin XIN pin XOUT pin 14 15 42pin 19 20 44pin 14 15
Figure 2.6.2 External Clock Circuit Example
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APPLICATIONS
2.7 Power-Saving Function
2.7 Power-Saving Function
2.7.1 Application Example of Stop Mode Power-Saving in Key-Input Waiting State POINT: When the CPU has no key input for the specified period in its key-input waiting state, the CPU enters the stop mode and reduces power dissipation by halting itself and its peripherals. Any key input, thereafter, generates a key-on wakeup interrupt request, and the CPU returns to the normal mode by accepting the request. SPECIFICATIONS: Port pin P00 is used as a key-input pin. When having no key input for the specified period, the CPU executes the STP instruction to enter the stop mode. Any key input generates a key-on wakeup interrupt request in the stop mode, and the CPU returns to the normal mode by accepting the request.
Figure 2.7.1 shows a connection example. Figure 2.7.2 shows an operation example in the key-input waiting state. Figure 2.7.3 shows a control procedure example of power-saving in key-input waiting state.
P00 Key input
7480 Group 7481 Group
Figure 2.7.1 Connection Example
STP instruction executed Key-input waiting state after the specified period XIN Internal clock
STP instruction execution cycle
Key-on wakeup interrupt request generated Stop mode state
Undefined XIN pin : High-impedance state
Key-on wakeup interrupt service routine executed
Oscillator start-up stabilizing time 2048 count of XIN pin input signal
Key input Port P0
Figure 2.7.2 Operation Example in Key-Input Waiting State
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2.7 Power-Saving Function
RESET(Note) Initialize SEI
Port P00 is set to input. Port P00 is pulled high. Set edge polarity selection register
b7 b0
1
EG (Address 00D416) Key-on wakeup
Set STP instruction operation control register (Writing 2 times) 1st writing
b7 b0
1 STPCON (Address 00DE16) 2nd writing
b7 b0
Writing `1' 0 STPCON (Address 00DE16) STP/WIT instruction valid
Processing
CLI Key input ? N N Specified period elapsed ? Y Key-on wakeup interrupt request bit 0 Key-on wakeup interrupt enable bit 1 Other interrupt enable bits 0 STP instruction execution Stop mode Y
System is returned to normal mode after the oscillation strat-up stabilization time elapsed.
Key-on wakeup interrupt service routine
Key input
Processing
RTI
The interrupt enable bit and timer 1 are returned to the state before the STP instruction is executed.
Note: State after system is released from reset * STP/WIT instructions invalid.
Processing
Figure 2.7.3 Control Procedure Example of Power-Saving in Key-Input Waiting State
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APPLICATIONS
2.7 Power-Saving Function
2.7.2 Application Example of Wait Mode Power-Saving in Serial I/O Receive Waiting State POINT: When serial I/O reception is not started in serial I/O receive enabled state, the CPU enters the wait mode and reduces power dissipation by halting itself. Then, when a serial I/O receive interrupt or a timer X interrupt is accepted after the specified period, and the CPU returns to the normal mode and terminates the communications. SPECIFICATIONS: Clock synchronous serial I/O reception * Synchronous clock: external clock input * SRDY signal output When serial I/O reception is not started in serial I/O receive enabled state, the CPU executes the WIT instruction to enter the wait mode. The CPU returns to the normal mode and terminates communications by either of the acceptance of the following interrupt sources: * Serial I/O receive interrupt * Timer X interrupt: receive wait time is counted in the timer mode
Figure 2.7.4 shows a connection example. Figure 2.7.5 shows an operation example in the serial I/O receive waiting state. Figure 2.7.6 shows a control procedure of power-saving.
TxD SCLK Port
P14/RxD P16/SCLK P17/SRDY
Microcomputer
7480 Group 7481 Group
Figure 2.7.4 Connection Example
WIT instruction executed Serial I/O receive ready completed XIN Internal clock
WIT instruction execution cycle
Serial I/O receive interrupt or timer X interrupt service routine executed Wait mode state
Figure 2.7.5 Operation Example in Serial I/O Receive Waiting State
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2.7 Power-Saving Function
RESET(Note 1) Initialize SEI
Set serial I/O control register
b7 b0
1 1 1 0 x 1 1 x SIOCON (Address 00E216) Synchronous clock: External clock input SRDY output Transmission disabled Reception enabled Clock synchronous serial I/O Serial I/O enabled
Set timer X mode register
b7 b0
x x x x 0 0 0 0 TXM (Address00F616) Timer * event count mode Writing to latch and timer simultaneously Timer X count source selected
Set STP instruction operation control register (Wring 2 times) 1st writing
b7 b0
Processing Timer X Reception wait time count value (Note 2) Serial I/O receive interrupt request bit 0 Timer X interrupt request bit 0 Serial I/O receive interrupt enable bit 1 Timer X interrupt enable bit 1 Other interrupt enable bits 0 Timer X count stop bit 0 Receive buffer register Dummy data WIT instruction executed Wait mode
2nd writing
b7
1 STPCON (Address 00DE16) Writing `1'
b0
0 STPCON (Address 00DE16) STP/WIT instruction valid
CLI
System is returned to normal mode after the oscillation start-up stabilization time elapsed.
Serial I/O receive interrupt service routine or timer X interrupt service routine
Reception is completed or reception waiting time elapses.
Processing
RTI The interrupt enable bit is returned to the state before the WIT instruction is executed. Serial I/O disabled Timer X count stop
Notes 1: State after system is released from reset * STP/WIT instructions invalid. 2: Write in order of low-order to high-order byte.
Processing
Figure 2.7.6 Control Procedure Example of Power-Saving
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2.8 Countermeasures against Noise
2.8 Countermeasures against Noise
Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 2.8.1 Shortest Wiring Length The wiring on a printed circuit board can be as an antenna which feeds noise into the microcomputer. The shorter the total wiring length (by mm unit), the less the possibility of noise insertion into a microcomputer. (1) Wiring for RESET Pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring (within 20mm). REASON The reset works to initialize a microcomputer. The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the microcomputer is released from reset before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
Noise
Reset circuit VSS
RESET VSS
Reset circuit VSS
RESET VSS
N.G.
7480 Group 7481 Group
O.K.
7480 Group 7481 Group
Figure 2.8.1 Wiring for RESET Pin
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2.8 Countermeasures against Noise
(2) Wiring for Clock I/O Pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. REASON A microcomputer's operation synchronizes with a clock generated by the oscillator (circuit). If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a malfunction or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer. (3) Wiring for VPP Pin of One Time PROM Version and EPROM Version (In the 7480 Group and 7481 Group, the VPP pin is also used as the P33 pin) Connect an approximately 5 k resistor to the VPP pin the shortest possible in series. Note: Even when a circuit which included an approximately 5 k resistor is used in the Mask ROM version, the microcomputer operates correctly. REASON The VPP pin of the One Time PROM and the EPROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the VPP pin is low to allow the electric current for writing flow into the PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal instruction codes or data are read from the built-in PROM, which may cause a program runaway.
Noise
7480 Group 7481 Group
XIN XOUT VSS
N.G.
7480 Group 7481 Group
XIN XOUT VSS
O.K.
Figure 2.8.2 Wiring for Clock I/O Pins
7480 Group 7481 Group
Approximately 5k P33/VPP
Figure 2.8.3 Wiring for VPP Pin of One Time PROM and EPROM Version
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2.8 Countermeasures against Noise
2.8.2 Connection of Bypass Capacitor across VSS Line and VCC Line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VCC line as follows: * Connect a bypass capacitor across the VSS pin and the VCC pin at equal length. * Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VCC line. * Connect the power source line to VSS pin and VCC pin through a bypass capacitor. 2.8.3 Connection of Bypass Capacitor across VSS Line and VREF Line Connect an approximately 0.01 F bypass capacitor across the VSS line and the VREF line as follows: * Connect a bypass capacitor across the VSS pin and the VREF pin at equal length. * Connect a bypass capacitor across the VSS pin and the VREF pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VREF line. 2.8.4 Wiring to Analog Input Pins * Connect an approximately 100 to 1 k resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. * Connect an approximately 0.1 to 1 F capacitor across the VSS pin and the analog input pin. Besides, connect the capacitor to the VSS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length. REASON Signals which is input in an analog input pin (such as an A-D converter input pin) are usually output signals from sensor. The sensor which detects a change of event is installed far from the printed circuit board with a microcomputer, the wiring to an analog input pin is longer necessarily. This long wiring functions as an antenna which feeds noise into the microcomputer, which causes noise to an analog input pin. If a capacitor between an analog input pin and the VSS pin is grounded at a position far away from the VSS pin, noise on the GND line may enter a microcomputer through the capacitor.
VCC
VCC
VSS
VSS
N.G.
O.K.
Figure 2.8.4 Bypass Capacitor across VSS Line and VCC Line
VREF
VREF
VSS
VSS
N.G.
O.K.
Figure 2.8.5 Bypass Capacitor across VSS Line and VREF Line
Noise
(Note)
Microcomputer Analog input pin
Thermistor
N.G.
O.K.
VSS
Note:The resistor is used for dividing resistance with a thermistor. Figure 2.8.6 Analog Signal Line and Resistor and Capacitor
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2.8 Countermeasures against Noise
2.8.5 Consideration for Oscillator Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping Oscillator Away from Large Current Signal Lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. REASON In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Keeping Oscillator Away from Signal Lines Where Potential Levels Change Frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. REASON Signal lines where potential levels change frequently (such as the CNTR pin line) may affect other lines at signal rising or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. (3) Oscillator Protection Using VSS Pattern As for a two-sided printed circuit board, print a VSS pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the VSS pattern to the microcomputer VSS pin with the shortest possible wiring. Besides, separate this VSS pattern from other VSS patterns. 7480 Group 7481 Group Mutual inductance M Large current GND Figure 2.8.7 Wiring for Large Current Signal Line XIN XOUT VSS
7480 Group 7481Group
Do not cross
CNTR XIN XOUT VSS
Figure 2.8.8 Wiring to Signal Line Where Potential Levels Change Frequently
An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example
7480 Group 7481 Group
XIN XOUT VSS
Separate the VSS line for oscillation from other VSS lines
Figure 2.8.9 VSS Patterns on Underside of Oscillator
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2.8 Countermeasures against Noise
2.8.6 Setup for I/O Ports Setup I/O ports using hardware and software as follows:
Data bus
O.K.
Direction register
Noise
* Connect a resistor of 100 or more to an I/O port in series. * As for an input port, read data several times by a program for checking whether input levels are equal or not. * As for an output port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. * Rewrite data to direction registers, and if necessary, pull-up control registers and port P4P5 input control register at fixed periods.
Noise
N.G.
Port latch I/O port pins
Figure 2.8.10 Setup For I/O Ports
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APPLICATIONS
2.8 Countermeasures against Noise
2.8.7 Providing of Watchdog Timer Function by Software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt service routine and the interrupt service routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
* Assigns a single byte of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition:
Main routine (SWDT) N CLI Main processing N (SWDT) =N? =N Interrupt service routine errors
Interrupt service routine (SWDT) (SWDT)--1 Interrupt processing (SWDT) 0? 0 >0 RTI Return Main routine errors
Figure 2.8.11 Watchdog Timer by Software
N+1 (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. * Watches the operation of the interrupt service routine by comparing the SWDT contents with counts of interrupt processing count after the initial value N has been set. * Detects that the interrupt service routine has failed and determines to branch to the program initialization routine for recovery processing in the following cases: If the SWDT contents do not change after interrupt processing * Decrements the SWDT contents by 1 at each interrupt processing. * Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). * Detects that the main routine has failed and determines to branch to the program initialization routine for recovery when the contents of the SWDT reach 0 or less by continuative decrement without initializing to the initial value N.
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2.9 Notes on Programming
2.9 Notes on Programming
2.9.1 Notes on Processor Status Register Initialization of Processor Status Register After system is released from reset, the contents of processor status register (PS) are undefined except for the I flag which is `1'. Therefore, flags which affect program execution must be initialized after system is released from reset. In particular, it is essential to initialize the T and D flags because they have an important effect on calculations. How to Refer Processor Status Register To refer the contents of the processor status register (PS), execute the PHP instruction once then read the contents of (S + 1). If necessary, execute the PLP instruction to return the PS to its original status. The NOP instruction should be executed after every PLP instruction.
Reset Flags of processor status register (PS) initializing
Main program
Figure 2.9.1 Initialization of Flags in PS
Stack area S S+1 Pushed PS
Figure 2.9.2 Stack Memory Contents after PHP Instruction Execution
PLP instruction NOP instruction
Figure 2.9.3 PLP Instruction Execution
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APPLICATIONS
2.9 Notes on Programming
2.9.2 Notes Concerning Decimal Operation Execution of Decimal Calculations The ADC and SBC are the only instructions which will yield proper decimal results in decimal mode. To calculate in decimal notation, set the decimal mode flag (D) to `1' with the SED instruction. After executing the ADC or SBC instruction, execute another instruction before executing the SEC, CLC, SED or CLD instruction.
Set D flag to `1' ADC,SBC instruction NOP instruction SEC,CLC,CLD instruction
Figure 2.9.4 Execution of Decimal Operation Note on Flags in Decimal Mode When decimal mode is selected, the values of three of the flags in the status register (the N, V, and Z flags) are invalid after the ADC or SBC instruction is executed. The carry flag (C) is set to `1' if a carry is generated as a result of the calculation, or is cleared to `0' if a borrow is generated. To determine whether a calculation has generated a carry, the C flag must be initialized to `1' before each calculation. 2.9.3 Notes on JMP Instruction When using the JMP instruction in indirect addressing mode, do not specify the last address on a page as an indirect address. Pages are sectioned every 256 addresses from address 0. For other notes, refer to each section.
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2.10 Differences between 7480 and 7481 Group, and 7477 and 7478 Group
2.10 Differences between 7480 and 7481 Group, and 7477 and 7478 Group
The 7480 Group and 7481 Group have almost the same functions as the 7477 Group and 7478 Group. However, take the following differences into consideration when using the former to replace the latter. 2.10.1 Functions Added to 7480 Group and 7481 Group Table 2.10.1 lists the functions added to the 7480 Group and 7481 Group. Table 2.10.1 Functions added to the 7480 Group and 7481 Group Added Function Bus Arbitration * Description In serial I/O communication of the bus-contention system, the level of the TxD pin is compared with that of the RxD pin. When there is a mismatch, a bus arbitration interrupt is generated to detect bus collision. The valid/invalid of the STP and WIT instructions is selectable by writing 2 times to the STP instruction operation control register. Watchdog timer returns program to the reset state if a runaway occurs. Each pin of ports P4 and P5 has a built-in clamping diode, by which voltages VCC or more can be applied. Note: In the 7480 Group, port P5 is not implemented.
STP and WIT Instruction Watchdog Timer Built-in Clamping Diode
* * *
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2.10 Differences between 7480 and 7481 Group, and 7477 and 478 Group
2.10.2 Functions Revised from 7477 Group and 7478 Group The functions of 7480 Group and 7481 Group whose specifications are revised from those of the 7477 Group and 7478 Group are listed in Table 2.10.2. Table 2.10.2 Functions Revised from 7477 Group and 7478 Group 7477 Group and 7478 Group RAM Sizes Port P4 7480 Group and 7481 Group M3747xM4 ..................................... 192 bytes M3748xM4 ........................................ 256 bytes M3747xM8/E8 ............................... 384 bytes M3748xM8/E8 .................................. 448 bytes * I/O port * I/O port * CMOS outputs * N-channel open-drain outputs * I n i n p u t m o d e , p u l l - u p t r a n s i s t o r s * Built-in clamping diodes connectable. * In input mode, P40-P43, P50-P53 pins have * Input port schmidt circuits. * Pull-up transistors connectable Note: The 7480 Group does not have P42, * P50, P51 serve as input pins for clock P43, and P50-P53 pins. generator. The 7480 Group and 7481 Group do Note: The 7477 Group does not have port not have the clock generator for timers. P5. CNTR Pins Timer Noise Margin CNTR0 and CNTR1 pins have the alternative CNTR0 and CNTR1 pins have the alternative functions of P32 and P33. functions of P40 and P41. Four 8-bit timers Two 8-bit timers Two 16-bit timers VIL: 0.25 VCC (Max.) VIH: 0.7 VCC (Min.) On port P3, P4, and P5 only. VIL: 0.4 VCC (Max.) VIH: 0.8 VCC (Min.) (at VCC = 4.5 V to 5.5 V) A-D Converter No VREF-off circuit To connect/not to connect between VREF and ladder resistors is selectable with a VREF-off circuit.
Port P5
Package
The M37478Mx/E8-XXXFP and M37478MxT/ The M37481Mx/E8-XXXFP and M37481MxT/ E8T-XXXFP packaged in 56P6N-A packages. E8T-XXXFP are packaged in 44P6N-A packages.
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APPLICATIONS
2.11 Application Circuit Examples
2.11 Application Circuit Examples
Figures 2.11.1 and 2.11.2 show two examples of application circuits using the 7480 Group and 7481 Group.
Igniter Frame detection Mode setting Thermistor 1 Thermistor 2 VR
For adjust
Port Port
Port Port Port
Electromagnetic valve 1 Electromagnetic valve 2 Water heater proportion valve Fan motor Water volume sensor Remote controller 1
Port
M37481M8T
IN P40/CNTR0 Port P41/CNTR1 Port PWM output Feedback PWM output Feedback
IN IN IN
Figure 2.11.1 Application Circuit to Hot-Water Supply Equipment
E2PROM
Port
P14/RxD P15/TxD
Driver
Remote controller 2 Remote controller 3
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2.11 Application Circuit Examples
Key code reception amplifier
Period measurement
P30/INT0
Programmable waveform Engine control signal output Igniter P41/CNTR1
M37481M8T
Crank input
P40/CNTR0 P31/INT1
Port
Electron carburetor
Sensor input
Throttle open degree Negative pressure sensor IN
E2PROM
Key input Ignition input
Port
Port
Port (For immobilizer)
Figure 2.11.2 Application Circuit to Motorcycle Single-Cylinder Engine
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2.11 Application Circuit Examples
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CHAPTER 3 APPENDICES
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 Control Registers Mask ROM Confirmation Forms ROM Programming Confirmation Forms Mark Specification Forms Package Outlines Machine Instructions List of Instruction Codes SFR Memory Map Pinouts
APPENDICES
3.1 Control Registers
3.1 Control Registers
Port Pi (i=0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi (Pi, i=0 to 5) [Addresses 00C016,00C216,00C416,00C616,00C816,00CA16]
b 0 1 2 3 4 5 6 7
Function When used as input ports (Ports P0 to P5) * At reading, input level of pin is read. * At writing, writing to port latch is performed and the pin state is not affected. When used as output ports (Ports P0, P1, P4, P5) * At reading, the last written value into the port latch is read. * At writing, the written value is output externally through a transistor.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R O O O O O O O O
W O O O O O O O O
Note: * In the 7480 Group, port P2 has only bits 0 to 3. The other bits are not implemented. (undefined at reading). * Port P3 has only bits 0 to 3. The other bits are not implemented (`0' at reading). * In the 7480 Group, port P4 has only bits 0 and 1. In the 7481 Group, port P4 has only bits 0 to 3. The other bits are not implemented. (bits 4 to 7: `0' at reading, bits 2 and 3 in the 7480 Group: undefined). * The 7480 Group does not have port P5. In the 7481 Group, port P5 has only bits 0 to 3. The other bits are not implemented. (`0' at reading).
Figure 3.1.1 Port Pi Registers (i = 0 to 5)
Port Pi direction register (i=0,1,4,5)
b7 b6 b5 b4 b3 b2 b1 b0 Port Pi direction register (PiD, i=0,1,4,5) [Addresses 00C116,00C316,00C916,00CB16] b 0 1 2 3 4 5 6 7 Name Port Pi direction register (Note) At reset 0 0 0 0 0 0 0 0 R O W O
Function 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode 0 : Input mode 1 : Output mode
O O O O O O O
O O O O O O O
Note: * In the 7480 Group, port P4 direction register has only bits 0 and 1. In the 7481 Group, port P4 direction register has only bits 0 to 3. The other bits are not implemented (bits 4 to 7: `0' at reading, bits 2 and 3 in the 7480 Group: undefined). * The 7480 Group does not have port P5 direction register. In the 7481 Group, port P5 has only bits 0 to 3. The other bits are not implemented (`0' at reading).
Figure 3.1.2 Port Pi Direction Registers (i = 0, 1, 4, 5)
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3.1 Control Registers
Port P0 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0 Port P0 pull-up control register (P0PCON) [Address 00D016]
b 0 1 2 3 4 5 6 7
Name P00 pull-up control bit P01 pull-up control bit P02 pull-up control bit P03 pull-up control bit P04 pull-up control bit P05 pull-up control bit P06 pull-up control bit P07 pull-up control bit
Function 0 : P00 No pull-up 1 : P00 Pull-up 0 : P01 No pull-up 1 : P01 Pull-up 0 : P02 No pull-up 1 : P02 Pull-up 0 : P03 No pull-up 1 : P03 Pull-up 0 : P04 No pull-up 1 : P04 Pull-up 0 : P05 No pull-up 1 : P05 Pull-up 0 : P06 No pull-up 1 : P06 Pull-up 0 : P07 No pull-up 1 : P07 Pull-up
At reset 0 0 0 0 0 0 0 0
R O O O O
W O O O O
O O O O
O O O O
Note: Pull-up control is valid when the corresponding port is set to the input mode.
Figure 3.1.3 Port P0 Pull-up Control Register
Port P1 pull-up control register
b7 b6 b5 b4 b3 b2 b1 b0 Port P1 pull-up control register (P1PCON) [Address 00D116]
b 0 1 2 3 4 5 6 7
Name P13-P10 pull-up control bit P17-P14 pull-up control bit
Function 0 : P10-P13 No pull-up 1 : P10-P13 Pull-up 0 : P14-P17 No pull-up 1 : P14-P17 Pull-up
At reset 0 0
Undefined Undefined Undefined Undefined Undefined Undefined
R O O
Undefined Undefined Undefined Undefined Undefined Undefined
W O O x x x x x x
Not implemented. Writing to these bits is disabled. These bits are undefined at reading.
Note: Pull-up control is valid only when the corresponding port is set to the input mode. When port pins P15-P17 are used as serial I/O pins, pull-up control of the corresponding port pins is invalid.
Figure 3.1.4 Port P1 Pull-up Control Register
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APPENDICES
3.1 Control Registers
Port P4P5 input control register
b7 b6 b5 b4 b3 b2 b1 b0
000000
Port P4P5 input control register (P4P5CON) [Address 00D216]
b 0 1 2 3 4 5 6 7
Name P42, P43 input control bit P5 input control bit
Function When the P42, P43 are used as the input port, set this bit to `1'. When the P5 is used as the input port, set this bit to `1'.
At reset 0 0 0 0 0 0 0 0
R O
W O
O 0 0 0 0 0 0
O x x x x x x
Not implemented. Writing to these bits is disabled. These bits are `0' at reading.
Note: 7480 Group does not have port pins P42, P43 and P5, so set bits 0 and 1 to `0'.
Figure 3.1.5 Port P4P5 Input Control Register
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3.1 Control Registers
Edge polarity selection register
b7 b6 b5 b4 b3 b2 b1 b0 Edge polarity selection register (EG) [Address 00D416]
b 0 1 2
Name INT0 edge selection bit INT1 edge selection bit CNTR0 edge selection bit 0 : Falling edge 1 : Rising edge
Function
At reset 0 0 0
R O O O
W O O O
3
CNTR1 edge selection bit
0 : Falling edge 1 : Rising edge 0: In event count mode, rising edge counted. : In pulse output mode, operation started at HIGH level output. : In pulse period measurement mode, a period from falling edge until falling edge measured. : In pulse width measurement mode, HIGH-level period measured. : In programmable one-shot output mode, one-shot HIGH pulse generated after operation started at LOW level output. : Interrupt request is generated by detecting falling edge. 1: In event count mode, falling edge counted. : In pulse output mode, operation started at LOW level output. : In pulse period measurement mode, a period from rising edge until rising edge measured. : In pulse width measurement mode, LOW-level period measured. : In programmable one-shot output mode, one-shot LOW pulse generated after operation started at HIGH level output. : Interrupt request is generated by detecting rising edge.
0
O
O
4 5
Not implemented. Writing to this bit is disabled. This bit is undefined at reading. 0 : P31/INT1 INT1 source selection bit at 1 : P00-P07 LOW level (for key-on wake-up) STP or WIT Not implemented. Writing to these bits are disabled. These bits are undefined at reading.
Undefined
Undefined
x
O
0
O
6 7
Undefined Undefined
Undefined Undefined
x x
Note: When setting bits 0 to 3, the interrupt request bit may be set to `1'. After setting the following, enable the interrupt. Disable interrupts Set the edge polarity selection register Set the interrupt request bit to `0'
Figure 3.1.6 Edge Polarity Selection Register
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APPENDICES
3.1 Control Registers
A-D control register
b7 b6 b5 b4 b3 b2 b1 b0 A-D control register (ADCON) [Address 00D916]
b 0
Name Analog input pin selection bits
b2 b1 b0
Function 0 0 0 : P20/IN0 0 0 1 : P21/IN1 0 1 0 : P22/IN2 0 1 1 : P23/IN3 1 0 0 : P24/IN4 1 0 1 : P25/IN5 1 1 0 : P26/IN6 1 1 1 : P27/IN7
At reset 0
R O
W O
1
0 (Note) 0
O
O
2
O
O
3 4
A-D conversion completion bit VREF connection selection bit
0 : Conversion in progress 1 : Conversion completed
0 : Disconnect between VREF pin and ladder resistor 1 : Connect between VREF pin and ladder resistor
1 0
O O
O
5 6 7
Not implemented. Writing to these bits is disabled. These bits are undefined at reading.
Undefined Undefined Undefined
Undefined Undefined Undefined
x x x
: The bit can be set to `0' by software, but cannot be set to `1'.
Note: Do not perform setting in the 7480 Group.
Figure 3.1.7 A-D Control Register
A-D conversion register
b7 b6 b5 b4 b3 b2 b1 b0 A-D conversion register (AD) [Address 00DA16]
b 0 1 2 3 4 5 6 7
Function Read-only register to store the A-D conversion result.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R O O O O O O O O
W
x x x x x x x x
Figure 3.1.8 A-D Conversion Register
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APPENDICES
3.1 Control Registers
STP instruction operation control register
b7 b6 b5 b4 b3 b2 b1 b0
0000000
STP instruction operation control register (STPCON) [Address 00DE16]
b 0 1 2 3 4 5 6 7
Name STP and WIT valid/invalid selection bit (Note)
Function 0 : STP/WIT instruction valid 1 : STP/WIT instruction invalid
At reset 1 0 0 0 0 0 0 0
R O 0 0 0 0 0 0 0
W O x x x x x x x
Not implemented. Writing to these bits is disabled. These bits are `0' at reading.
Note: The STP and WIT instructions are invalid after the system is released from reset. When using these instructions, set STP and WIT valid/invalid selection bit of the STP instruction operation control register to `1', then set this bit to `0'. (Writing twice successively) When not using the STP and WIT instructions, set this bit to `1' either once or twice.
Figure 3.1.9 STP Instruction Operation Control Register
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APPENDICES
3.1 Control Registers
Transmit/Receive buffer register
b7 b6 b5 b4 b3 b2 b1 b0 Transmit/Receive buffer register (TB/RB) [Address 00E016]
b 0 1 2 3 4 5 6 7
Function In transmission: Transmit data is transferred to the transmit shift register by writing transmit data. In reception: When data is stored completely in the receive shift register, the receive data is transferred to this register.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R
W
Note
Note: In transmission, this register is a write-only register. In reception, this register is a read-only register.
Figure 3.1.10 Transmit/Receive Buffer Register
Serial I/O status register
b7 b6 b5 b4 b3 b2 b1 b0
1
Serial I/O status register (SIOSTS) [Address 00E116]
b 0 1 2 3 4 5 6 7
Name Transmit buffer empty flag (TBE) Receive buffer full flag (RBF) Transmit shift completion flag (TSC) Overrun error flag (OE) Parity error flag (PE) Framing error flag (FE) Summing error flag (SE) This bit is fixed to `1'.
Function 0 : Buffer full 1 : Buffer empty 0 : Buffer empty 1 : Buffer full 0 : Transmit shift in progress 1 : Transmit shift completed 0 : No error 1 : Overrun error 0 : No error 1 : Parity error 0 : No error 1 : Framing error 0 : OE U PE U FE=0 1 : OE U PE U FE=1
At reset 0 0 0 0 0 0 0 1
R O
W
x x x x x x x x
O O O O
O O 1
Note: b4 and b5 are valid only in UART
Figure 3.1.11 Serial I/O Status Register
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3.1 Control Registers
Serial I/O control register
b7 b6 b5 b4 b3 b2 b1 b0 Serial I/O control register (SIOCON) [Address 00E216] b 0 1 Name BRG count source selection bit (CSS) Serial I/O synchronous clock selection bit (SCS) Function 0 : f(XIN)/4 1 : f(XIN)/16
when clock synchronous serial I/O is selected
At reset 0 0
R O O
W O O
0 : BRG output/4 1 : External clock input when UART is selected 0 : BRG output/16 1 : External clock input/16 0 : P17 pin 1 : SRDY output pin 0 : Interrupt occurs when transmit
buffer is empty.
2 3
SRDY output enable bit (SRDY) Transmit interrupt source selection bit (TIC)
0 0
O O
O O
1 : Interrupt occurs when transmit shift
operation is completed.
4 5 6 7
Transmit enable bit (TE) Receive enable bit (RE) Serial I/O mode selection bit (SIOM) Serial I/O enable bit (SIOE)
0 : Transmit disabled 1 : Transmit enabled 0 : Receive disabled 1 : Receive enabled 0 : Asynchronous serial I/O (UART) 1 : Clock synchronous serial I/O 0 : Serial I/O disabled 1 : Serial I/O enabled
0 0 0 0
O O
O O O
O O
O
Figure 3.1.12 Serial I/O Control Register
UART control register
b7 b6 b5 b4 b3 b2 b1 b0
1111
UART control register (UARTCON) [Address 00E316] b 0 1 2 3 4 5 6 7 Name Character length selection bit (CHAS) Parity enable bit (PARE) Parity selection bit (PARS) Stop bit length selection bit (STPS) These bits are fixed to `1'. 0 : 8 bits 1 : 7 bits 0 : Parity disabled 1 : Parity enabled 0 : Even parity 1 : Odd parity 0 : 1 stop bit 1 : 2 stop bits Function At reset
0
R
O
W O
0 0 0 1 1 1 1
O O O 1 1 1 1
O O O
x x x x
Figure 3.1.13 UART Control Register
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APPENDICES
3.1 Control Registers
Baud rate generator
b7 b6 b5 b4 b3 b2 b1 b0 Baud rate generator (BRG) [Address 00E416]
b 0 1 2 3 4 5 6 7
Function * 8-bit timer for baud rate generation of serial I/O. * Valid only when BRG output divided by 4 or 16 is selected as synchronous clock.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R O O O O O O O O
W O O O O O O O O
Figure 3.1.14 Baud Rate Generator
Bus collision detection control register
b7 b6 b5 b4 b3 b2 b1 b0
0000000
Bus collision detection control register (BUSARBCON) [Address 00E516] R O 0 0 0 0 0 0 0 W O
b 0 1 2 3 4 5 6 7
Name Bus collision detection enable bit
Function 0 : Collision detection invalid 1 : Collision detection valid
At reset 0 0 0 0 0 0 0 0
Not implemented. Writing to these bits is disabled. These bits are `0' at reading.
x x x x x x x
Figure 3.1.15 Bus Collision Detection Control Register
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APPENDICES
3.1 Control Registers
Watchdog timer H
b7 b6 b5 b4 b3 b2 b1 b0 Watchdog timer H (WDTH) [Address 00EF16]
b 0 1 2 3 4 5 6 7
Function The high-order count value of watchdog timer is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note
Note: The following value is set by writing arbitrary data. * watchdog timer L `7F16' * watchdog timer H `FF16'
Figure 3.1.16 Watchdog Timer H
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APPENDICES
3.1 Control Registers
Timer X (Timer X latch)
b7 b6 b5 b4 b3 b2 b1 b0 Timer X (high-order) (TXH) [Address 00F116] b7 b6 b5 b4 b3 b2 b1 b0 Timer X (low-order) (TXL) [Address 00F016] Function The low-order count value of timer X is indicated.
b 0 1 2 3 4 5 6 7
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note 1
b 0 1 2 3 4 5 6 7
Function The high-order count value of timer X is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note 1
Notes 1: Do not write to these bits in pulse period measurement mode or pulse width measurement mode. 2: When b3 of timer X mode register is `0', writing to latch and timer is simultaneously performed. When b3 is `1', writing to only latch is performed. 3: When reading/writing from/to timer X, read/write from/to both high-order and low-order bytes. At reading, read the high-order byte and the low-order byte in this order. At writing, write the low-order byte and the high-order byte in this order.
Figure 3.1.17 Timer X
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3.1 Control Registers
Timer Y (Timer Y latch)
b7 b6 b5 b4 b3 b2 b1 b0 Timer Y (high-order) (TYH) [Address 00F316] b7 b6 b5 b4 b3 b2 b1 b0 Timer Y (low-order) (TYL) [Address 00F216]
b 0 1 2 3 4 5 6 7
Function The low-order count value of timer Y is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note 1
b 0 1 2 3 4 5 6 7
Function The high-order count value of timer Y is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W
Note 1
Notes 1: Do not write to these bits in pulse period measurement mode or pulse width measurement mode. 2: When b3 of timer Y mode register is `0', writing to latch and timer is simultaneously performed. When b3 is `1', writing to only latch is performed. 3: When reading/writing from/to timer Y, read/write from/to both high-order and low-order bytes. At reading, read the high-order byte and the low-order byte in this order. At writing, write the low-order byte and the high-order byte in this order.
Figure 3.1.18 Timer Y
Timer 1 (Timer 1 latch)
b7 b6 b5 b4 b3 b2 b1 b0 Timer1 (T1) [Address 00F416]
b 0 1 2 3 4 5 6 7
Function The timer 1 count value is indicated.
At reset 1 1 1 1 1 1 1 1
R O O O O O O O O
W O O O O O O O O
Figure 3.1.19 Timer 1
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APPENDICES
3.1 Control Registers
Timer 2 (Timer 2 latch)
b7 b6 b5 b4 b3 b2 b1 b0 Timer 2 (T2) [Address 00F516]
b 0 1 2 3 4 5 6 7
Function The timer 2 count value is indicated.
At reset
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R O O O O O O O O
W O O O O O O O O
Figure 3.1.20 Timer 2
Timer X mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer X mode register (TXM) [Address 00F616]
b 0
Name Timer X operating mode bits
b2 b1 b0
Function
0 0 0 : Timer * event count mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot output mode 1 1 0 : PWM mode 1 1 1 : Not available
At reset 0
R O
W O
1
0
O
O
2
0
O
O
3 4 5
Timer X write control bit Output level latch Timer X trigger selection bit
0 : Writing to both latch and timer 1 : Writing to latch only 0 : LOW output from CNTR0 pin 1 : HIGH output from CNTR0 pin 0 : Timer X free run in programmable waveform generation mode 1 : Trigger occurrence (input signal of INT0 pin) and timer X start in programmable waveform generation mode
b7 b6
0 0 0
O O O
O O O
6 7
Timer X count source selection bits
0 0 : f(XIN)/2 0 1 : f(XIN)/8 1 0 : f(XIN)/16 1 1 : Input from CNTR0 pin
0 0
O O
O O
Figure 3.1.21 Timer X Mode Register
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7480 Group and 7481 Group User's Manual
APPENDICES
3.1 Control Registers
Timer Y mode register
b7 b6 b5 b4 b3 b2 b1 b0 Timer Y mode register (TYM) [Address 00F716] b 0 Name
b2 b1 b0
Function 0 0 0 : Timer * event count mode 0 0 1 : Pulse output mode 0 1 0 : Pulse period measurement mode 0 1 1 : Pulse width measurement mode 1 0 0 : Programmable waveform generation mode 1 0 1 : Programmable one-shot output mode 1 1 0 : PWM mode 1 1 1 : Not available
At reset
0
R O
W O
Timer Y operating mode bits
1
0
O
O
2
0
O
O
3 4 5
Timer Y write control bit 0 : Writing to both latch and timer 1 : Writing to latch only Output level latch Timer Y trigger selection bit 0 : LOW output from CNTR1 pin 1 : HIGH output from CNTR1 pin 0 : Timer Y free run in programmable waveform generation mode 1 : Trigger occurrence (input signal of INT1 pin) and timer Y start in programmable waveform generation mode
b7 b6
0 0 0
O O O
O O O
6 7
Timer Y count source selection bits
0 0 : f(XIN)/2 0 1 : f(XIN)/8 1 0 : f(XIN)/16 1 1 : Input from CNTR1 pin
0 0
O O
O O
Figure 3.1.22 Timer Y Mode Register
Timer XY control register
b7 b6 b5 b4 b3 b2 b1 b0
000000
Timer XY control register (TXYCON) [Address 00F816]
b 0 1 2 3 4 5 6 7
Name Timer X stop control bit Timer Y stop control bit
Function 0 : Count operation 1 : Count stop 0 : Count operation 1 : Count stop
At reset 1 1 0 0 0 0 0 0
R O O 0 0 0 0 0 0
W O O
Not implemented. Writing to these bits is disabled. These bits are `0' at reading.
x x x x x x
Figure 3.1.23 Timer XY Control Register
7480 Group and 7481 Group User's Manual
3-15
APPENDICES
3.1 Control Registers
Timer 1 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Timer 1 mode register (T1M) [Address 00F916]
b 0 1 2 3 4 5 6 7
Name Timer 1 stop control bit Timer 1 operation mode bit
Function 0 : Count operation 1 : Count stop 0 : Timer mode 1 : Programmable waveform generation mode
At reset 0 0 0 0 0 0 0 0
R O O 0 0 O 0 O O
W O O
Not implemented. Writing to these bits is disabled. These bits are `0' at reading. Output level latch 0 : LOW output from T0 pin 1 : HIGH output from T0 pin
x x
O
Not implemented. Writing to this bit is disabled. This bit is `0' at reading. Timer 1 count source selection bits
b7 b6
x
O O
0 0 : f(XIN)/8 0 1 : f(XIN)/64 1 0 : f(XIN)/128 1 1 : f(XIN)/256
Figure 3.1.24 Timer 1 Mode Register
Timer 2 mode register
b7 b6 b5 b4 b3 b2 b1 b0
0
00
Timer 2 mode register (T2M) [Address 00FA16]
b 0 1 2 3 4 5 6 7
Name Timer 2 stop control bit Timer 2 operation mode bit
Function 0 : Count operation 1 : Count stop 0 : Timer mode 1 : Programmable waveform generation mode
At reset 0 0 0 0 0 0 0 0
R O O 0 0 O 0 O O
W O O
Not implemented. Writing to these bits is disabled. These bits are `0' at reading. Output level latch 0 : LOW output from T1 pin 1 : HIGH output from T1 pin
x x
O
Not implemented. Writing to this bit is disabled. This bit is `0' at reading. Timer 2 count source selection bits
b7 b6
x
O O
0 0 : f(XIN)/8 0 1 : f(XIN)/64 1 0 : f(XIN)/128 1 1 : f(XIN)/256
Figure 3.1.25 Timer 2 Mode Register
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7480 Group and 7481 Group User's Manual
APPENDICES
3.1 Control Registers
CPU mode register
b7 b6 b5 b4 b3 b2 b1 b0
00
CPU mode register (CPUM) [Address 00FB16]
b 0 1 2 3 4 5 6 7
Name Fix these bits to `0'. Stack page selection bit (Note) Watchdog timer L count source selection bit
Function
At reset 0
R O O O O
Undefined
W 0 0 O O x x O x
0 : Zero page 1 : 1 page 0 : f(XIN)/8 1 : f(XIN)/16
0 0 0
Undefined
Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Not implemented. Writing to this bit is disabled. This bit is undefined at reading. Clock division ratio selection bit 0 : f(XIN)/2 (high-speed mode) 1 : f(XIN)/8 (medium-speed mode)
Undefined
Undefined
0
Undefined
O
Undefined
Not implemented. Writing to this bit is disabled. This bit is undefined at reading.
Note: In the products whose RAM size is 192 bytes or less, set this bit to `0'.
Figure 3.1.26 CPU Mode Register
7480 Group and 7481 Group User's Manual
3-17
APPENDICES
3.1 Control Registers
Interrupt request register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 1 (IREQ1) [Address 00FC16]
b 0 1 2 3 4 5 6 7
Name
Function
At reset
0
R O O O O O O O O
W
Timer X interrupt request bit 0 : No interrupt request 1 : Interrupt request Timer Y interrupt request bit 0 : No interrupt request 1 : Interrupt request Timer 1 interrupt request bit 0 : No interrupt request 1 : Interrupt request Timer 2 interrupt request bit 0 : No interrupt request 1 : Interrupt request Serial I/O receive interrupt request bit Serial I/O transmit interrupt request bit Bus arbitration interrupt request bit A-D conversion completion interrupt request bit 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request

0 0 0 0 0 0 0
: The bit can be set to `0' by software, but cannot be set to `1'.
Figure 3.1.27 Interrupt Request Register 1
Interrupt request register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt request register 2 (IREQ2) [Address 00FD16]
b 0 1 2 3 4 5 6 7
Name INT0 interrupt request bit INT1 interrupt request bit
Function 0 : No interrupt request 1 : Interrupt request 0 : No interrupt request 1 : Interrupt request
At reset 0 0 0 0
Undefined Undefined Undefined Undefined
R O
W
x x x x
O O O
Undefined Undefined Undefined Undefined
CNTR0 interrupt request bit 0 : No interrupt request 1 : Interrupt request CNTR1 interrupt request bit 0 : No interrupt request 1 : Interrupt request Not implemented. Writing to these bits is disabled. These bits are undefined at reading.
: The bit can be set to `0' by software, but cannot be set to `1'.
Figure 3.1.28 Interrupt Request Register 2
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7480 Group and 7481 Group User's Manual
APPENDICES
3.1 Control Registers
Interrupt control register 1
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1) [Address 00FE16]
b 0 1 2 3 4 5 6 7
Name Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit Serial I/O receive interrupt enable bit Serial I/O transmit interrupt enable bit Bus arbitration interrupt enable bit A-D conversion completion interrupt enable bit
Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset 0 0 0 0 0 0 0 0
R O O O O O O O O
W O O O O O O O O
Figure 3.1.29 Interrupt Control Register 1
Interrupt control register 2
b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2) [Address 00FF16]
b 0 1 2 3 4 5 6 7
Name INT0 interrupt enable bit INT1 interrupt enable bit CNTR0 interrupt enable bit CNTR1 interrupt enable bit
Function 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled
At reset 0 0 0 0
Undefined Undefined Undefined Undefined
R O O O O
Undefined Undefined Undefined Undefined
W O O O O
Not implemented. Writing to these bits are disabled. These bits are undefined at reading.
x x x x
Figure 3.1.30 Interrupt Control Register 2
7480 Group and 7481 Group User's Manual
3-19
APPENDICES
3.2 Mask ROM Confirmation Forms
3.2 Mask ROM Confirmation Forms
GZZ-SH09-84B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37480M2T-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37480M2T-XXXFP (hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 2FFF16 300016
ROM (4K) codes of the name of the product `M37480M2T-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 6FFF16 700016
ROM (4K) codes of the name of the product `M37480M2T-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 EFFF16 F00016
ROM (4K) codes of the name of the product `M37480M2T-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37480M2T-' to addresses 000016 to 000F16. ASCII codes `M37480M2T-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `0' = 3016 `M' = 4D16 `2' = 3216
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16
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7480 Group and 7481 Group User's Manual
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-84B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M2T-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command V=
.BYTE
27128 $C000
`M37480M2T-' .BYTE
27256 V= $8000
`M37480M2T-' .BYTE
27512 V= $0000
`M37480M2T-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M2T-XXXSP, 32P2W-A for M37480M2T-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-21
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-85B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37480M4-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37480M4-XXXFP (hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 1FFF16 200016
ROM (8K) codes of the name of the product `M37480M4-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 5FFF16 600016
ROM (8K) codes of the name of the product `M37480M4-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 DFFF16 E00016
ROM (8K) codes of the name of the product `M37480M4-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37480M4-' to addresses 000016 to 000F16. ASCII codes `M37480M4-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `0' = 3016 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
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7480 Group and 7481 Group User's Manual
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-85B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M4-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 V= $C000 .BYTE `M37480M4-' 27256 V= $8000 .BYTE `M37480M4-' 27512 V= $0000 .BYTE `M37480M4-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M4-XXXSP, 32P2W-A for M37480M4-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-23
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-86B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37480M4T-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37480M4T-XXXFP (hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 1FFF16 200016
ROM (8K) codes of the name of the product `M37480M4T-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 5FFF16 600016
ROM (8K) codes of the name of the product `M37480M4T-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 DFFF16 E00016
ROM (8K) codes of the name of the product `M37480M4T-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37480M4T-' to addresses 000016 to 000F16. ASCII codes `M37480M4T-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `0' = 3016 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16
3-24
7480 Group and 7481 Group User's Manual
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-86B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M4T-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command V=
.BYTE
27128 $C000
`M37480M4T-' .BYTE
27256 V= $8000
`M37480M4T-' .BYTE
27512 V= $0000
`M37480M4T-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M4T-XXXSP, 32P2W-A for M37480M4T-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-25
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-87B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37480M8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37480M8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37480M8-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37480M8-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37480M8-' to addresses 000016 to 000F16. ASCII codes `M37480M8-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `0' = 3016 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
3-26
7480 Group and 7481 Group User's Manual
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-87B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M8-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command 27256 V= $8000 .BYTE `M37480M8-' 27512 V= $0000 .BYTE `M37480M8-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M8-XXXSP, 32P2W-A for M37480M8-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-27
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-88B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37480M8T-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37480M8T-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37480M8T-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37480M8T-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37480M8T-' to addresses 000016 to 000F16. ASCII codes `M37480M8T-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `0' = 3016 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16
3-28
7480 Group and 7481 Group User's Manual
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-88B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480M8T-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command
.BYTE
27256 V= $8000
`M37480M8T-'
27512 V=
.BYTE
$0000
`M37480M8T-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (32P4B for M37480M8T-XXXSP, 32P2W-A for M37480M8T-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-29
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-78B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37481M2T-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37481M2T-XXXFP (hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 2FFF16 300016
ROM (4K) codes of the name of the product `M37481M2T-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 6FFF16 700016
ROM (4K) codes of the name of the product `M37481M2T-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 EFFF16 F00016
ROM (4K) codes of the name of the product `M37481M2T-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37481M2T-' to addresses 000016 to 000F16. ASCII codes `M37481M2T-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `1' = 3116 `M' = 4D16 `2' = 3216
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16
3-30
7480 Group and 7481 Group User's Manual
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-78B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M2T-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command V=
.BYTE
27128 $C000
`M37481M2T-' .BYTE
27256 V= $8000
`M37481M2T-' .BYTE
27512 V= $0000
`M37481M2T-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M2T-XXXSP, 44P6N-A for M37481M2T-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-31
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-79B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37481M4-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37481M4-XXXFP (hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 1FFF16 200016
ROM (8K) codes of the name of the product `M37481M4-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 5FFF16 600016
ROM (8K) codes of the name of the product `M37481M4-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 DFFF16 E00016
ROM (8K) codes of the name of the product `M37481M4-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37481M4-' to addresses 000016 to 000F16. ASCII codes `M37481M4-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `1' = 3116 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
3-32
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APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-79B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M4-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command 27128 V= $C000 .BYTE `M37481M4-' 27256 V= $8000 .BYTE `M37481M4-' 27512 V= $0000 .BYTE `M37481M4-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M4-XXXSP, 44P6N-A for M37481M4-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-33
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-80B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37481M4T-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37481M4T-XXXFP (hexadecimal notation)
27128
EPROM address 000016 Area for ASCII 000F16 001016 1FFF16 200016
ROM (8K) codes of the name of the product `M37481M4T-'
27256
EPROM address 000016 Area for ASCII 000F16 001016 5FFF16 600016
ROM (8K) codes of the name of the product `M37481M4T-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 DFFF16 E00016
ROM (8K) codes of the name of the product `M37481M4T-'
3FFF16
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37481M4T-' to addresses 000016 to 000F16. ASCII codes `M37481M4T-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `1' = 3116 `M' = 4D16 `4' = 3416
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16
3-34
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APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-80B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M4T-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the start address of the assembler source program. EPROM type The pseudo-command V=
.BYTE
27128 $C000
`M37481M4T-' .BYTE
27256 V= $8000
`M37481M4T-' .BYTE
27512 V= $0000
`M37481M4T-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M4T-XXXSP, 44P6N-A for M37481M4T-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-35
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-81B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37481M8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37481M8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37481M8-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37481M8-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37481M8-' to addresses 000016 to 000F16. ASCII codes `M37481M8-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `1' = 3116 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
3-36
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APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-81B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M8-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command 27256 V= $8000 .BYTE `M37481M8-' 27512 V= $0000 .BYTE `M37481M8-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M8-XXXSP, 44P6N-A for M37481M8-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-37
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-82B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37481M8T-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37481M8T-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37481M8T-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37481M8T-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37481M8T-' to addresses 000016 to 000F16. ASCII codes `M37481M8T-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `1' = 3116 `M' = 4D16 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16
3-38
7480 Group and 7481 Group User's Manual
APPENDICES
3.2 Mask ROM Confirmation Forms
GZZ-SH09-82B<56A0>
Mask ROM number
740 FAMILY MASK ROM CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481M8T-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command 27256 V= $8000 .BYTE `M37481M8T-' 27512 V= $0000 .BYTE `M37481M8T-'
Note : If the name of the product written to the EPROMs does not match the name of the mask confirmation, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered fill out the appropriate mark specification form (42P4B for M37481M8T-XXXSP, 44P6N-A for M37481M8T-XXXFP) and attach to the mask ROM confirmation form.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-39
APPENDICES
3.3 ROM Programming Confirmation Forms
3.3 ROM Programming Confirmation Forms
GZZ-SH09-91B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37480E8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37480E8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37480E8-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37480E8-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37480E8-' to addresses 000016 to 000F16. ASCII codes `M37480E8-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `0' = 3016 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
3-40
7480 Group and 7481 Group User's Manual
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-91B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480E8-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command 27256 V= $8000 .BYTE `M37480E8-' 27512 V= $0000 .BYTE `M37480E8-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37480E8-XXXSP or the 32P2W-A Mark Specification Form for the M37480E8-XXXFP.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-41
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-92B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37480E8T-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37480E8T-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37480E8T-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37480E8T-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37480E8T-' to addresses 000016 to 000F16. ASCII codes `M37480E8T-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `0' = 3016 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16
3-42
7480 Group and 7481 Group User's Manual
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-92B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37480E8T-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command
.BYTE
27256 V= $8000
`M37480E8T-'
27512 V=
.BYTE
$0000
`M37480E8T-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37480E8T-XXXSP or the 32P2W-A Mark Specification Form for the M37480E8T-XXXFP.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-43
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-89B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37481E8-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37481E8-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37481E8-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37481E8-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37481E8-' to addresses 000016 to 000F16. ASCII codes `M37481E8-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `1' = 3116 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16 FF16
3-44
7480 Group and 7481 Group User's Manual
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-89B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481E8-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command 27256 V= $8000 .BYTE `M37481E8-' 27512 V= $0000 .BYTE `M37481E8-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37481E8-XXXSP or the 44P6N-A Mark Specification Form for the M37481E8-XXXFP.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-45
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-90B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM MITSUBISHI ELECTRIC
Receipt
SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP
Date: Section head Supervisor signature signature
Note : Please fill in all items marked g. ) Issuance signature Company name Date issued Date: TEL ( Submitted by Supervisor
g Customer
g 1. Confirmation Specify the name of the product being ordered and the type of EPROMs submitted. Three EPROMs are required for each pattern (Check @ in the appropriate box). If at least two of the three sets of EPROMs submitted contain identical data, we will produce ROM programming based on this data. We shall assume the responsibility for errors only if the ROM data on the products we produce differs from this data. Thus, extreme care must be taken to verify the data in the submitted EPROMs. Microcomputer name : M37481E8T-XXXSP Checksum code for entire EPROM EPROM type (indicate the type used) M37481E8T-XXXFP (hexadecimal notation)
27256
EPROM address 000016 Area for ASCII 000F16 001016 3FFF16 400016
ROM (16K) codes of the name of the product `M37481E8T-'
27512
EPROM address 000016 Area for ASCII 000F16 001016 BFFF16 C00016
ROM (16K) codes of the name of the product `M37481E8T-'
7FFF16
FFFF16
(1) Set "FF16" in the shaded area. (2) Write the ASCII codes that indicates the name of the product `M37481E8T-' to addresses 000016 to 000F16. ASCII codes `M37481E8T-' are listed on the right. The addresses and data are in hexadecimal notation.
Address 000016 000116 000216 000316 000416 000516 000616 000716
`M' = 4D16 `3' = 3316 `7' = 3716 `4' = 3416 `8' = 3816 `1' = 3116 `E' = 4516 `8' = 3816
Address 000816 000916 000A16 000B16 000C16 000D16 000E16 000F16
` T ' = 5416 ` - ' = 2D16 FF16 FF16 FF16 FF16 FF16 FF16
3-46
7480 Group and 7481 Group User's Manual
APPENDICES
3.3 ROM Programming Confirmation Forms
GZZ-SH09-90B<56A0>
ROM number
740 FAMILY ROM PROGRAMMING CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M37481E8T-XXXSP/FP MITSUBISHI ELECTRIC
Recommend to writing the following pseudo-command to the assembler source file : EPROM type The pseudo-command 27256 V= $8000 .BYTE `M37481E8T-' 27512 V= $0000 .BYTE `M37481E8T-'
Note : If the name of the product written to the EPROMs does not match the name of the ROM programming confirmation form, the ROM processing is disabled. Write the data correctly.
g 2. Mark specification Mark specification must be submitted using the correct form for the package being ordered. Please submit the shrink DIP package Mark Specification Form (only for built-in One Time PROM microcomputer) for the M37481E8T-XXXSP or the 44P6N-A Mark Specification Form for the M37481E8T-XXXFP.
g 3. Comments
7480 Group and 7481 Group User's Manual
3-47
APPENDICES
3.4 Mark Specification Forms
3.4 Mark Specification Forms
32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM
3-48
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APPENDICES
3.4 Mark Specification Forms
32P2W (32-PIN SOP) MARK SPECIFICATION FORM
7480 Group and 7481 Group User's Manual
3-49
APPENDICES
3.4 Mark Specification Forms
42P4B (42-PIN SHRINK DIP) MARK SPECIFICATION FORM
3-50
7480 Group and 7481 Group User's Manual
APPENDICES
3.4 Mark Specification Forms
44P6N (44-PIN QFP) MARK SPECIFICATION FORM
Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark
#3
@3 @2
Mitsubishi lot number (6-digit)
#4
Mitsubishi IC catalog name
$4 q !1
!2
B. Customer's Parts Number + Mitsubishi Catalog Name
#3 #4 @3 @2
Customer's parts number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name and Mitsubishi lot number Note4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required.
$4 q !1
!2
Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer's parts number can be up to 7 characters : Only 0 ~ 9, A ~ Z,+,-, , (, ), &, (c), * (period), and (comma) are usable.
,
C. Special Mark Required
#3 #4 @3 @2
$4 q !1
!2
Note1 : If the special mark is to be printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit ) and mask ROM number (3-digit) are always marked. 2 : If the customer's trade mark logo must be used in the special mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required
3 : The standard Mitsubishi font is used for all characters except for a logo.
7480 Group and 7481 Group User's Manual
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APPENDICES
3.5 Package Outlines
3.5 Package Outlines
32P2W-A
32P4B
3-52
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APPENDICES
3.5 Package Outlines
42P4B
44P6N-A
7480 Group and 7481 Group User's Manual
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APPENDICES
3.6 Machine Instructions
3.6 Machine instructions
Addressing mode Symbol Function Details IMP OP n ADC (Note 1) (Note 5) When T = 0 AA+M+C When T = 1 M(X) M(X) + M + C Adds the carry, accumulator and memory contents. The results are entered into the accumulator. Adds the contents of the memory in the address indicated by index register X, the contents of the memory specified by the addressing mode and the carry. The results are entered into the memory at the address indicated by index register X. "AND's" the accumulator and memory contents. The results are entered into the accumulator. "AND's" the contents of the memory of the address indicated by index register X and the contents of the memory specified by the addressing mode. The results are entered into the memory at the address indicated by index register X. Shifts the contents of accumulator or contents of memory one bit to the left. The low order bit of the accumulator or memory is cleared and the high order bit is shifted into the carry flag. Branches when the contents of the bit specified in the accumulator or memory is "0". Branches when the contents of the bit specified in the accumulator or memory is "1". Branches when the contents of carry flag is "0". Branches when the contents of carry flag is "1". Branches when the contents of zero flag is "1". 24 3 2 IMM # OP n 69 2 A # OP n 2 BIT, A # OP n ZP # OP n 65 3 BIT, ZP # OP n 2 #
ASL C
7
0
0
BBC (Note 4) BBS (Note 4) BCC (Note 4) BCS (Note 4) BEQ (Note 4) BIT
Ab or Mb = 0?
Ab or Mb = 1?
C = 0?
C = 1?
Z = 1? V
A
M
BMI (Note 4) BNE (Note 4) BPL (Note 4) BRA
N = 1?
Z = 0?
N = 0? PC PC offset B1 M(S) PCH SS-1 M(S) PCL SS-1 M(S) PS SS-1 PCL ADL PCH ADH
BRK
3-54
V
When T = 1 M(X) M(X)
V
AND (Note 1)
When T = 0 AA M M
29 2
2
25 3
2
0A 2
1
06 5
2
13 4 + 20i 03 4 + 20i
2
17 5 + 20i 07 5 + 20i
3
2
3
"AND's" the contents of accumulator and memory. The results are not entered anywhere. Branches when the contents of negative flag is "1". Branches when the contents of zero flag is "0".
Branches when the contents of negative flag is "0". Jumps to address specified by adding offset to the program counter. Executes a software interrupt. 00 7 1
7480 Group and 7481 Group User's Manual
APPENDICES
3.6 Machine Instructions
Addressing mode ZP, X OP n 75 4 ZP, Y # OP n 2 ABS # OP n 6D 4 ABS, X # OP n 3 7D 5 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7
Processor status register 6 V V 5 T * 4 B * 3 D * 2 I * 1 Z Z 0 C C
# OP n 3 79 5
# OP n 3
# OP n 61 6
# OP n 2 71 6
# OP n 2
N N
35 4
2
2D 4
3 3D 5
3 39 5
3
21 6
2 31 6
2
N
*
*
*
*
*
Z
*
16 6
2
0E 6
3 1E 7
3
N
*
*
*
*
*
Z
C
*
*
*
*
*
*
*
*
* 90 2
*
*
*
*
*
*
*
2
*
*
*
*
*
*
*
*
B0 2
2
*
*
*
*
*
*
*
*
F0 2
2
*
*
*
*
*
*
*
*
2C 4
3
M7 M6 *
*
*
*
Z
*
30 2
2
*
*
*
*
*
*
*
*
D0 2
2
*
*
*
*
*
*
*
*
10 2
2
*
*
*
*
*
*
*
*
80 4
2
*
*
*
*
*
*
*
*
*
*
*
1
*
1
*
*
7480 Group and 7481 Group User's Manual
3-55
APPENDICES
3.6 Machine Instructions
Addressing mode Symbol Function Details IMP OP n BVC (Note 4) BVS (Note 4) CLB V = 0? Branches when the contents of overflow flag is "0". Branches when the contents of overflow flag is "1". Clears the contents of the bit specified in the accumulator or memory to "0". Clears the contents of the carry flag to "0". 18 2 1 1B 2 + 20i 1 1F 5 + 20i 2 IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n #
V = 1? Ab or Mb 0 C0 D0 I0 T0 V0 When T = 0 A-M When T = 1 M(X) - M MM X-M
__
CLC
CLD
Clears the contents of decimal mode flag to "0". Clears the contents of interrupt disable flag to "0". Clears the contents of index X mode flag to "0". Clears the contents of overflow flag to "0".
D8 2
1
CLI
58 2
1
CLT
12 2
1
CLV
B8 2
1
CMP (Note 3)
Compares the contents of accumulator and memory. Compares the contents of the memory specified by the addressing mode with the contents of the address indicated by index register X. Forms a one's complement of the contents of memory, and stores it into memory. Compares the contents of index register X and memory. Compares the contents of index register Y and memory. Decrements the contents of the accumulator or memory by 1. Decrements the contents of index register X CA 2 by 1. Decrements the contents of index register Y by 1. Divides the 16-bit data that is the contents of M (zz + x + 1) for high byte and the contents of M (zz + x) for low byte by the accumulator. Stores the quotient in the accumulator and the 1's complement of the remainder on the stack. "Exclusive-ORs" the contents of accumulator and memory. The results are stored in the accumulator. "Exclusive-ORs" the contents of the memory specified by the addressing mode and the contents of the memory at the address indicated by index register X. The results are stored into the memory at the address indicated by index register X. Increments the contents of accumulator or memory by 1. Increments the contents of index register X by 1. Increments the contents of index register Y by 1. E8 2 1 88 2 1
C9 2
2
C5 3
2
COM
44 5
2
CPX
E0 2
2
E4 3
2
CPY
Y-M A A - 1 or MM-1 XX-1 YY-1 A (M(zz + X + 1), M(zz + X)) / A M(S) 1's complememt of Remainder SS-1 When T = 0 - A AVM When T = 1 - M(X) M(X) V M
C0 2
2
C4 3
2
DEC
1A 2
1
C6 5
2
DEX
DEY
1
DIV
EOR (Note 1)
49 2
2
45 3
2
INC
A A + 1 or MM+1 XX+1 YY+1
3A 2
1
E6 5
2
INX
INY
C8 2
1
3-56
7480 Group and 7481 Group User's Manual
APPENDICES
3.6 Machine Instructions
Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n 2 # 7
Processor status register 6 V * 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n
# OP n
# OP n
# OP n
# OP n 50 2
N *
70 2
2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
0
*
*
*
*
0
*
*
*
*
*
*
*
*
0
*
*
*
*
0
*
*
*
*
*
* D5 4 CD 4
0
*
*
*
*
*
*
2
3 DD 5
3 D9 5
3
C1 6
2 D1 6
2
N
*
*
*
*
*
Z
C
N EC 4
*
*
*
*
*
Z
*
3
N
*
*
*
*
*
Z
C
CC 4
3
N
*
*
*
*
*
Z
C
D6 6
2
CE 6
3 DE 7
3
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N E2 16 2
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
55 4
2
4D 4
3 5D 5
3 59 5
3
41 6
2 51 6
2
N
*
*
*
*
*
Z
*
F6 6
2
EE 6
3 FE 7
3
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
7480 Group and 7481 Group User's Manual
3-57
APPENDICES
3.6 Machine Instructions
Addressing mode Symbol Function Details IMP OP n JMP If addressing mode is ABS PCL ADL PCH ADH If addressing mode is IND PCL M (ADH, ADL) PCH M (ADH, ADL + 1) If addressing mode is ZP, IND PCL M(00, ADL) PCH M(00, ADL + 1) M(S) PCH SS-1 M(S) PCL SS-1 After executing the above, if addressing mode is ABS, PCL ADL PCH ADH if addressing mode is SP, PCL ADL PCH FF If addressing mode is ZP, IND, PCL M(00, ADL) PCH M(00, ADL + 1) When T = 0 AM When T = 1 M(X) M M nn XM YM Jumps to the specified address. IMM # OP n A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n #
JSR
After storing contents of program counter in stack, and jumps to the specified address.
LDA (Note 2)
Load accumulator with contents of memory. Load memory indicated by index register X with contents of memory specified by the addressing mode. Load memory with immediate value.
A9 2
2
A5 3
2
LDM
3C 4
3
LDX
Load index register X with contents of memory. Load index register Y with contents of memory. 0 C Shift the contents of accumulator or memory to the right by one bit. The low order bit of accumulator or memory is stored in carry, 7th bit is cleared. Multiplies the accumulator with the contents of memory specified by the zero page X addressing mode and stores the high byte of the result on the stack and the low byte in the accumulator. No operation. EA 2 1
A2 2
2
A6 3
2
LDY
A0 2
2
A4 3
2
LSR
7 0
4A 2
1
46 5
2
MUL
M(S) * A A ! M(zz + X) SS-1
NOP
PC PC + 1
ORA (Note 1)
When T = 0 AAVM When T = 1 M(X) M(X) V M
"Logical OR's" the contents of memory and accumulator. The result is stored in the accumulator. "Logical OR's" the contents of memory indicated by index register X and contents of memory specified by the addressing mode. The result is stored in the memory specified by index register X.
09 2
2
05 3
2
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7480 Group and 7481 Group User's Manual
APPENDICES
3.6 Machine Instructions
Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n 4C 3 ABS, X # OP n 3 ABS, Y IND ZP, IND # OP n 3 B2 4 IND, X IND, Y REL SP # OP n # 7
Processor status register 6 V * 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n
# OP n 6C 5
# OP n 2
# OP n
# OP n
N *
20 6
3
02 7
2
22 5
2
*
*
*
*
*
*
*
*
B5 4
2
AD 4
3 BD 5
3 B9 5
3
A1 6
2 B1 6
2
N
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
B6 4 B4 4 56 6
2 AE 4 AC 4 4E 6
3
BE 5
3
N
*
*
*
*
*
Z
*
2
3 BC 5
3
N
*
*
*
*
*
Z
*
2
3 5E 7
3
0
*
*
*
*
*
Z
C
62 15 2
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
15 4
2
0D 4
3 1D 5
3 19 5
3
01 6
2 11 6
2
N
*
*
*
*
*
Z
*
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APPENDICES
3.6 Machine Instructions
Addressing mode Symbol Function Details IMP OP n PHA M(S) A SS-1 Saves the contents of the accumulator in memory at the address indicated by the stack pointer and decrements the contents of stack pointer by 1. Saves the contents of the processor status register in memory at the address indicated by the stack pointer and decrements the contents of the stack pointer by 1. Increments the contents of the stack pointer by 1 and restores the accumulator from the memory at the address indicated by the stack pointer. Increments the contents of stack pointer by 1 and restores the processor status register from the memory at the address indicated by the stack pointer. Shifts the contents of the memory or accumulator to the left by one bit. The high order bit is shifted into the carry flag and the carry flag is shifted into the low order bit. Shifts the contents of the memory or accumulator to the right by one bit. The low order bit is shifted into the carry flag and the carry flag is shifted into the high order bit. Rotates the contents of memory to the right by 4 bits. 48 3 IMM # OP n 1 A # OP n BIT, A # OP n ZP # OP n BIT, ZP # OP n #
PHP
M(S) PS SS-1
08 3
1
PLA
SS+1 A M(S)
68 4
1
PLP
SS+1 PS M(S)
28 4
1
ROL
7
0 C
2A 2
1
26 5
2
ROR
7 C
0
6A 2
1
66 5
2
RRF
7 SS+1 PS M(S) SS+1 PCL M(S) SS+1 PCH M(S) SS+1 PCL M(S) SS+1 PCH M(S)
0
82 8
2
RTI
Returns from an interrupt routine to the main routine.
40 6
1
RTS
Returns from a subroutine to the main routine.
60 6
1
SBC (Note 1) (Note 5)
When T = 0 _ AA-M-C When T = 1 _ M(X) M(X) - M - C
Subtracts the contents of memory and complement of carry flag from the contents of accumulator. The results are stored into the accumulator. Subtracts contents of complement of carry flag and contents of the memory indicated by the addressing mode from the memory at the address indicated by index register X. The results are stored into the memory of the address indicated by index register X. Sets the specified bit in the accumulator or memory to "1". Sets the contents of the carry flag to "1". 38 2 1
E9 2
2
E5 3
2
SEB
Ab or Mb 1 C1 D1 I1 T1
0B 2 + 20i
1
0F 5 + 20i
2
SEC
SED
Sets the contents of the decimal mode flag to "1". Sets the contents of the interrupt disable flag to "1". Sets the contents of the index X mode flag to "1".
F8 2
1
SEI
78 2
1
SET
32 2
1
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7480 Group and 7481 Group User's Manual
APPENDICES
3.6 Machine Instructions
Addressing mode ZP, X OP n ZP, Y # OP n ABS # OP n ABS, X # OP n ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7
Processor status register 6 V * 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n
# OP n
# OP n
# OP n
# OP n
N *
*
*
*
*
*
*
*
*
N
*
*
*
*
*
Z
*
(Value saved in stack)
36 6
2
2E 6
3 3E 7
3
N
*
*
*
*
*
Z
C
76 6
2
6E 6
3 7E 7
3
N
*
*
*
*
*
Z
C
*
*
*
*
*
*
*
*
(Value saved in stack)
*
*
*
*
*
*
*
*
F5 4
2
ED 4
3 FD 5
3 F9 5
3
E1 6
2 F1 6
2
N
V
*
*
*
*
Z
C
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
1
*
*
*
*
1
*
*
*
*
*
*
*
*
1
*
*
*
*
1
*
*
*
*
*
7480 Group and 7481 Group User's Manual
3-61
APPENDICES
3.6 Machine Instructions
Addressing mode Symbol Function Details IMP OP n STA MA Stores the contents of accumulator in memory. IMM # OP n A # OP n BIT, A # OP n ZP # OP n 85 4 42 2 BIT, ZP # OP n 2 #
STP MX MY XA YA M = 0? XS AX SX AY
Stops the oscillator.
1
STX
Stores the contents of index register X in memory. Stores the contents of index register Y in memory. Transfers the contents of the accumulator to AA 2 index register X. Transfers the contents of the accumulator to index register Y. Tests whether the contents of memory are "0" or not. Transfers the contents of the stack pointer to BA 2 index register X. Transfers the contents of index register X to the accumulator. Transfers the contents of index register X to the stack pointer. Transfers the contents of index register Y to the accumulator. Stops the internal clock. 8A 2 1 A8 2 1
86 4 84 4
2
STY
2
TAX
TAY
1
TST
64 3
2
TSX
TXA
1
TXS
9A 2
1
TYA
98 2
1
WIT Notes 1 2 3 4 5
C2 2
1
: The number of cycles "n" is increased by 3 when T is 1. : The number of cycles "n" is increased by 2 when T is 1. : The number of cycles "n" is increased by 1 when T is 1. : The number of cycles "n" is increased by 2 when branching has occurred. : N, V, and Z flags are invalid in decimal operation mode.
3-62
7480 Group and 7481 Group User's Manual
APPENDICES
3.6 Machine Instructions
Addressing mode ZP, X OP n 95 5 ZP, Y # OP n 2 ABS # OP n 8D 5 ABS, X # OP n 3 9D 6 ABS, Y IND ZP, IND # OP n IND, X IND, Y REL SP # OP n # 7
Processor status register 6 V * 5 T * 4 B * 3 D * 2 I * 1 Z * 0 C *
# OP n 3 99 6
# OP n 3
# OP n 81 7
# OP n 2 91 7
# OP n 2
N *
*
*
*
*
*
*
*
*
96 5
2 8E 5
3
*
*
*
*
*
*
*
*
94 5
2
8C 5
3
*
*
*
*
*
*
*
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
N
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
N
*
*
*
*
*
Z
*
*
*
*
*
*
*
*
*
Symbol IMP IMM A BIT, A ZP BIT, ZP ZP, X ZP, Y ABS ABS, X ABS, Y IND ZP, IND IND, X IND, Y REL SP C Z I D B T V N
Contents Implied addressing mode Immediate addressing mode Accumulator or Accumulator addressing mode Accumulator bit relative addressing mode Zero page addressing mode Zero page bit relative addressing mode Zero page X addressing mode Zero page Y addressing mode Absolute addressing mode Absolute X addressing mode Absolute Y addressing mode Indirect absolute addressing mode Zero page indirect absolute addressing mode Indirect X addressing mode Indirect Y addressing mode Relative addressing mode Special page addressing mode Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag X-modified arithmetic mode flag Overflow flag Negative flag + - V - V - X Y S PC PS PCH PCL ADH ADL FF nn M V
Symbol
Contents Addition Subtraction Logical OR Logical AND Logical exclusive OR Negation Shows direction of data flow Index register X Index register Y Stack pointer Program counter Processor status register 8 high-order bits of program counter 8 low-order bits of program counter 8 high-order bits of address 8 low-order bits of address FF in Hexadecimal notation Immediate value Memory specified by address designation of any addressing mode Memory of address indicated by contents of index register X Memory of address indicated by contents of stack pointer Contents of memory at address indicated by ADH and ADL, in ADH is 8 high-order bits and ADL is 8 low-order bits. Contents of address indicated by zero page ADL 1 bit of accumulator 1 bit of memory Opcode Number of cycles Number of bytes
M(X) M(S) M(ADH, ADL)
M(00, ADL) Ab Mb OP n #
7480 Group and 7481 Group User's Manual
3-63
APPENDICES
3.7 List of Instruction Codes
3.7 List of Instruction Codes
D3 - D0 Hexadecimal notation 0
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
D7 - D4
0
1
2
3 BBS 0, A BBC 0, A BBS 1, A BBC 1, A BBS 2, A BBC 2, A BBS 3, A BBC 3, A BBS 4, A BBC 4, A BBS 5, A
4
5 ORA ZP ORA ZP, X AND ZP AND ZP, X EOR ZP EOR ZP, X ADC ZP ADC ZP, X STA ZP STA ZP, X LDA ZP LDA ZP, X CMP ZP CMP ZP, X SBC ZP SBC ZP, X
6 ASL ZP ASL ZP, X ROL ZP ROL ZP, X LSR ZP LSR ZP, X ROR ZP ROR ZP, X STX ZP STX ZP, Y LDX ZP LDX ZP, Y DEC ZP DEC ZP, X INC ZP INC ZP, X
7 BBS 0, ZP BBC 0, ZP BBS 1, ZP BBC 1, ZP BBS 2, ZP BBC 2, ZP BBS 3, ZP BBC 3, ZP BBS 4, ZP BBC 4, ZP BBS 5, ZP BBC 5, ZP BBS 6, ZP BBC 6, ZP BBS 7, ZP BBC 7, ZP
8
9 ORA IMM
A ASL A
B SEB 0, A CLB 0, A SEB 1, A CLB 1, A SEB 2, A CLB 2, A SEB 3, A CLB 3, A SEB 4, A CLB 4, A SEB 5, A CLB 5, A SEB 6, A CLB 6, A SEB 7, A CLB 7, A
C
D ORA ABS
E ASL ABS
F SEB 0, ZP
0000
BRK
ORA JSR IND, X ZP, IND ORA IND, Y AND IND, X AND IND, Y EOR IND, X EOR IND, Y CLT JSR SP SET
--
PHP
--
0001
1
BPL JSR ABS BMI
-- BIT ZP -- COM ZP -- TST ZP -- STY ZP STY ZP, X LDY ZP LDY ZP, X CPY ZP -- CPX ZP --
CLC
ORA DEC ABS, Y A AND IMM AND ABS, Y EOR IMM EOR ABS, Y ADC IMM ADC ABS, Y -- ROL A INC A LSR A -- ROR A --
-- BIT ABS LDM ZP JMP ABS -- JMP IND -- STY ABS -- LDY ABS
ORA ASL CLB ABS, X ABS, X 0, ZP AND ABS ROL ABS SEB 1, ZP
0010
2
PLP
0011
3
SEC
AND ROL CLB ABS, X ABS, X 1, ZP EOR ABS LSR ABS SEB 2, ZP
0100
4
RTI
STP
PHA
0101
5
BVC
--
CLI
EOR LSR CLB ABS, X ABS, X 2, ZP ADC ABS ROR ABS SEB 3, ZP
0110
6
RTS
MUL ADC IND, X ZP, X ADC IND, Y STA IND, X STA IND, Y LDA IND, X -- RRF ZP -- LDX IMM
PLA
0111
7
BVS
SEI
ADC ROR CLB ABS, X ABS, X 3, ZP STA ABS STA ABS, X LDA ABS STX ABS -- LDX ABS SEB 4, ZP CLB 4, ZP SEB 5, ZP
1000
8
BRA
DEY
TXA
1001
9
BCC LDY IMM BCS CPY IMM BNE CPX IMM BEQ
TYA
STA TXS ABS, Y LDA IMM TAX
1010
A
TAY
1011
B
JMP LDA BBC IND, Y ZP, IND 5, A CMP IND, X CMP IND, Y WIT BBS 6, A BBC 6, A BBS 7, A BBC 7, A
CLV
LDA TSX ABS, Y CMP IMM CMP ABS, Y SBC IMM SBC ABS, Y DEX
LDY LDA LDX CLB ABS, X ABS, X ABS, Y 5, ZP CPY ABS -- CPX ABS -- CMP ABS DEC ABS SEB 6, ZP
1100
C
INY
1101
D
--
CLD
--
CMP DEC CLB ABS, X ABS, X 6, ZP SBC ABS INC ABS SEB 7, ZP
1110
E
DIV SBC IND, X ZP, X SBC IND, Y --
INX
NOP
1111
F
SED
--
SBC INC CLB ABS, X ABS, X 7, ZP
3-byte instruction 2-byte instruction 1-byte instruction
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7480 Group and 7481 Group User's Manual
APPENDICES
3.8 SFR Memory Map
3.8 SFR Memory Map
Figure 3.8.1 shows the SFR memory map.
00C016 00C116 00C216 00C316 00C416 00C516 00C616 00C716 00C816 00C916 00CA16 00CB16 00CC16 00CD16 00CE16 00CF16 00D016 00D116 00D216 00D316 00D416 00D516 00D616 00D716 00D816 00D916 00DA16 00DB16 00DC16 00DD16 00DE16 00DF16
Port P0 register (P0) Port P0 direction register (P0D) Port P1 register (P1) Port P1 direction register (P1D) Port P2 register (P2) Port P3 register (P3) Port P4 register (P4) Port P4 direction register (P4D) Port P5 register (P5) Port P5 direction register (P5D)
Port P0 pull-up control register (P0PCON) Port P1 pull-up control register (P1PCON) Port P4P5 input control register (P4P5CON) Edge polarity selection register (EG)
A-D control register (ADCON) A-D conversion register (AD)
STP instruction operation control register (STPCON)
00E016 00E116 00E216 00E316 00E416 00E516 00E616 00E716 00E816 00E916 00EA16 (Note) 00EB16 00EC16 00ED16 00EE16 00EF16 00F016 00F116 00F216 00F316 00F416 00F516 00F616 00F716 00F816 00F916 00FA16 00FB16 00FC16 00FD16 00FE16 00FF16
Transmit/receive buffer register (TB/RB) Serial I/O status register (SIOSTS) Serial I/O control register (SIOCON) UART control register (UARTCON) Baud rate generator (BRG) Bus collision detection control register (BUSARBCON)
Watchdog timer H (WDTH) Timer X low-order (TXL) Timer X high-order (TXH) Timer Y low-order (TYL) Timer Y high-order (TYH) Timer 1 (T1) Timer 2 (T2) Timer X mode register (TXM) Timer Y mode register (TYM) Timer XY control register (TXYCON) Timer 1 mode register (T1M) Timer 2 mode register (T2M) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Interrupt control register 2 (ICON2)
Note: These registers are not allocated in the 7480 Group.
Figure 3.8.1 SFR Memory Map
7480 Group and 7481 Group User's Manual
3-65
APPENDICES
3.9 Pinouts
3.9 Pinouts
Figures 3.9.1 and 3.9.2 show the pinouts of the 7480 Group and 7481 Group.
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET VCC
Outline 32P4B V1
M37480M8-XXXSP M37480M8T-XXXSP M37480E8-XXXSP M37480E8T-XXXSP
P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
P07 P06 P05 P04 P03 P02 P01 P00 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET VCC
Outline 32P2W-A V2 V 1: The M37480M2T-XXXSP, M37480M4-XXXSP and M37480M4T-XXXSP are also included in the 32P4B packages, respectively. All of these products are pin-compatible. 2: The M37480M2T-XXXFP, M37480M4-XXXFP and M37480M4T-XXXFP are also included in the 32P2W-A packages, respectively. All of these products are pin-compatible. Note: The only differences between the 32P4B package product and the 32P2W-A package product are package outline and absolute maximum ratings.
Figure 3.9.1 Pinout of 7480 Group (top view)
3-66
7480 Group and 7481 Group User's Manual
M37480M8-XXXFP M37480M8T-XXXFP M37480E8-XXXFP M37480E8T-XXXFP
APPENDICES
3.9 Pinouts
P53 P17/SRDY P16/SCLK P15/TXD P14/RXD P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1 P20/IN0 VREF XIN XOUT VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
P52 P07 P06 P05 P04 P03 P02 P01 P00 P43 P42 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1 P30/INT0 RESET P51 P50 VCC
Outline 42P4B V1 42S1B-A (M37481E8SS)
31
33
27
30
28
32
P04 P05 P06 P07 P52 VSS P53 P17/SRDY P16/SCLK P15/TXD P14/RXD
29
26
25
24
23
P03 P02 P01 P00 P43 P42 P41/CNTR1 P40/CNTR0 P33 P32 P31/INT1
M37481M8-XXXSP M37481M8T-XXXSP M37481E8-XXXSP M37481E8T-XXXSP M37481E8SS
34 35 36 37 38 39 40 41 42 43 44
22 21 20
M37481M8-XXXFP M37481M8T-XXXFP M37481E8-XXXFP M37481E8T-XXXFP
19 18 17 16 15 14 13 12
P30/INT0 RESET P51 P50 VCC VSS AVSS XOUT XIN VREF P20/IN0
V 1: The M37481M2T-XXXSP, M37481M4-XXXSP and M37481M4T-XXXSP are also included in the 42P4B packages, respectively. All of these products are pin-compatible. 2: The M37481M2T-XXXFP, M37481M4-XXXFP and M37481M4T-XXXFP are also included in the 44P6N-A packages, respectively. All of these products are pin-compatible. Note: The only differences between the 42P4B package product and the 44P6N-A package product are package outline, absolute maximum ratings and the fact that the 44P6N-A package product has the AVss pin.
Figure 3.9.2 Pinout of 7481 Group (top view)
P13/T1 P12/T0 P11 P10 P27/IN7 P26/IN6 P25/IN5 P24/IN4 P23/IN3 P22/IN2 P21/IN1
Outline 44P6N-A
V2
7480 Group and 7481 Group User's Manual
10
11
1
2
4
7
3
6
5
8
9
3-67
APPENDICES
3.9 Pinouts
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3-68
7480 Group and 7481 Group User's Manual
MITSUBISHI SEMICONDUCTORS USER'S MANUAL 7480 Group 7481 Group
Nov. First Edition 1997 Editioned by Committee of editing of Mitsubishi Semiconductor USER'S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division
This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
(c)1996 MITSUBISHI ELECTRIC CORPORATION
User's Manual 7480 Group 7481 Group
Printed in Japan (ROD) (c) 1997 MITSUBISHI ELECTRIC CORPORATION
New publication, effective Nov. 1997. Specifications subject to change without notice.
REVISION DESCRIPTION LIST
Rev. No. 1.0 First Edition
7480 GROUP AND 7481 GROUP USER'S MANUAL
Revision Description Rev. date 971130
(1/1)
GRADE
A
MESC TECHNICAL NEWS
The following errors exist in the 7480 Group and 7481 Group User's Manual. Please refer to the corrected information as shown below.
No.M740-14-9712
Additional information of 7480/7481 Group (Rev.A)
Corrected information of 7480 Group and 7481 Group User's Manual (Rev.A) Page Error Correct 1-192 Figure 1.21.5
Conditions: 25C, f(XIN)=8 MHz (with a ceramic resonator) in wait mode 3.0
Power source current ICC [mA]
High-speed mode 2.0
Medium-speed mode 1.0
0.0 2.0 3.0 4.0 5.0 6.0 7.0
Power source voltage VCC [V]
: Corrected points
2-24 Section 2.3.3 SPECIFICATIONS
LAN communication format: Simplified SAE J1850 (PWM system)
LAN communication format: Simplified SAE* J1850 (PWM system) *SAE: Society of Automotive Engineers
(1/1)


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